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BF707 memory performance

Category: Hardware
Product Number: adsp-bf707

How many clock cycles to access the TCM and On-Chip RAM?

The I/D cache should be 1 clock (0-wait state).

I would expect the TCM to be 1 clock (0-wait state) as well.

Thread Notes

  • Hi Brian,

    In ADSP-BF707, L1 memory provides a modified Harvard architecture, allowing up to four core memory accesses per clock cycle (one 64-bit instruction fetch, two 32-bit data loads, and one pipelined 32-bit data store).

    When there are no collisions while accessing different or single data block of L1 memory, the following L1 data traffic could occur in a single core clock cycle:

    • Two 32-bit data accesses (two loads or one load and one store)
    • One DMA I/O, up to 32 bits
    • One 64-bit cache fill or victim access

    We are looking into the Target Command Mode (TCM) performance as well and will get back to you.

    Regards,

    Divya.P

  • Hi Brian,

    To calculate the cycle count in BF-707 you can refer to the snippet available in the mentioned CCES path below: 

    CrossCore® Embedded Studio 2.11.1 > Blackfin® Development Tools Documentation > C/C++ Compiler and Library Manual for Blackfin® Processors > DSP Run-Time Library > DSP Run-Time Library Guide > Measuring Cycle Counts

    Cycle Count:

    #include <cycle_count.h>
    #include <stdio.h>

    extern int
    main(void)
    {
    cycle_t start_count;
    cycle_t final_count;

    START_CYCLE_COUNT(start_count);
    Some_Function_Or_Code_To_Measure();
    STOP_CYCLE_COUNT(final_count,start_count);

    PRINT_CYCLES("Number of cycles: ",final_count);
    }

    Please confirm that you have added -DDO_CYCLE_COUNTS compile-time switch. If this switch is not specified, the macros are replaced by empty statements and have no effect on the program.


    Please refer attached image for your reference.

                                 

    You can navigate as follows.
    Project Properties-> C/C++ Build-> Settings-> Tool Settings-> CrossCore SHARC C/C++ Compiler-> Preprocessor-> Preprocessor Definitions-> DO_CYCLE_COUNTS.

    You can also refer to the EE-376 note:"ADSP-BF70x Blackfin+TM Processor System Optimization Techniques" for more information on performance.
    ADSP-BF70x Blackfin+ Processor System Optimization Techniques (EE-376) (analog.com)

    Regards,
    Divya.P