Problems using BF512 and S1D13506

Hi-

I moved this question to the Blackfin Processors community.  Please continue the discussion here.

Thanks,

AndyR

EngineerZone Community Manager

Hi,

Couple of thoughts if it can help:

• I was searching for any details of this controller, and the first hit was the page from Epson that lists this under discontinued items:
  

       http://vdc.epson.com/index.php?option=com_docman&task=cat_view&gid=82&Itemid=99

       This is valid as far as the App Note is concerned, since it was written nearly 8 years ago.

• In BF51x, each bank has a total of 1MB capacity, whereas BF535 can support up to 64MB for each bank. If you need to use up to 4MB, then you need to enable all the banks, and also mux them together to the chip select of your device, similar to the evaluation board example with Flash memory.
  

• BF51x has 16 bit external data port while BF535 has 32-bit with packing option for 16-bit, so the address pins connections are more direct for former case (see flash example in EZ-KIT). The byte enables are still valid when writing in to upper or lower bytes of a 16-bit data. There is still no ADDR0 in BF51x.
  

• Make sure the RDYEN bits are enabled for ARDY.
  

• See if the controller is going in reset or something and if the CLKOUT from Blackfin is proper.
  

• You might want to check if the data written in to some block of registers, is going in to other - something that might indicate wrong configuration or connection.
  

• Probe all lines at the controller end, and see if anything is wrong as far as the AMI bus signals are concerned. The waveforms should match the examples in hardware manual, and timing in the datasheet.
  

Regards

Prasanth.

Hi Prasanth,

    Thanks for your advices, but the problem is still not fixed.

    We have verified we use 4 banks in the BF512  and the RDYEN is enabled.

    We configure the Async like this:

*pEBIU_AMGCTL = 0x00ff;
ssync();

*pEBIU_AMBCTL0 = 0x33173317;
*pEBIU_AMBCTL1 = 0x33173317;
ssync();

  

    and also configured the GPIOs related to the connection.

    The phenomenon now is when we read data from the chip we got the last data we write, that is:

    If we write three data to the different registers, and then we read the first register, we will get the last data back.

 

    We are confused and don't know if the hardware is wrong or the software configuration is wrong.

    Do you have any ideas about this issue? Thanks!

Best Regards,

Nicolas,

Hi Nicolas

You could contact Support with further details such as schematics (as you said in message). Please use this link to reach Support team:

http://forms.analog.com/Form_Pages/support/dsp/dspSupport.asp

Regards

Prasanth.

This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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EZ Admin