BF547  - Configuring SPORT0 Primary & Secondary to work with AD73311L x 4

Hi

Do you actually see dat / clk / fs coming on the lines at the device probing end (so there are no MUX related to board level issues)? Can you post the SPORT configuration, and a connection block diagram? Do the devices connected to primary work, when primary alone is turned on, with data in consecutive locations? How do you see that these devices actually fail? Instead of relying on their analog end, is there a way to read back the programmed control data?

Regards

Prasanth. 

Hi Prasanth

Sport configuration :

_InitSport0:   
    link 4;

    P0.H = HI(SPORT0_RCR1);
    P0.L = LO(SPORT0_RCR1);
    R0 = 0x0400;
    W[ P0 ] = R0.L;
    ssync;
   
    P0.L = LO(SPORT0_RCR2);
    R0 = SLEN_16_ENSEC; // SPORT WORD length = 16 & Enable Secondary side of Sport
    W[ P0 ] = R0.L;

    ssync;

    P0.L = LO(SPORT0_TCR1);
    R0 = 0x400;
    W[ P0 ] = R0.L;

    ssync;

    P0.L = LO(SPORT0_TCR2);
    R0 = SLEN_16_ENSEC;// SPORT WORD length = 16 & Enable Secondary side of Sport
    W[ P0 ] = R0.L;
    ssync;

    p0 = [fp+4];
    unlink;   
    jump(p0);

_InitSport0.END:

The  words for the control registers of the codecs are :

    #define ZER_CH2   0x0000
    #define ZER_CH1   0x0000
    #define CRS_CH2   0x8880
    #define CRS_CH1   0x8080
    #define CRA_CH2   0x8813    //mixed mode
    #define CRA_CH1   0x8013    //mixed mode
    #define CRB_CH2   0x890f
    #define CRB_CH1   0x810f
    #define CRC_CH2   0x8A79
    #define CRC_CH1   0x8279
    #define CRD_CH2   0x8B00  
    #define CRD_CH1   0x8300  
    #define CRE_CH2   0x8C34 
    #define CRE_CH1   0x8434 
    #define CRF_CH2   0x8D80
    #define CRF_CH1   0x8580

   segment("data3")short Codec1TxRegs_SEC_PRI[32] =
    {               
                       
                        CRS_CH2/*Pri*/,CRS_CH2 /*Sec*/,CRS_CH1/*Pri*/,CRS_CH1 ,/*Sec*/ //reset
                       
                        CRF_CH2/*Pri*/,CRF_CH2 /*Sec*/,CRF_CH1/*Pri*/,CRF_CH1,/*Sec*/ //,CRF_CH1/*Pri*/,CRF_CH1 /*Sec*/,
                       
                        CRE_CH2/*Pri*/,CRE_CH2 /*Sec*/,CRE_CH1/*Pri*/,CRE_CH1,/*Sec*/ //,CRE_CH1/*Pri*/,CRE_CH1 /*Sec*/,
                       
                        CRD_CH2/*Pri*/,CRD_CH2 /*Sec*/,CRD_CH1/*Pri*/,CRD_CH1,/*Sec*/ //,CRD_CH1/*Pri*/,CRD_CH1 /*Sec*/,
                       
                        CRC_CH2/*Pri*/,CRC_CH2 /*Sec*/,CRC_CH1/*Pri*/,CRC_CH1,/*Sec*/ //,CRC_CH1/*Pri*/,CRC_CH1 /*Sec*/,
                                               
                        CRB_CH2/*Pri*/,CRB_CH2 /*Sec*/,CRB_CH1/*Pri*/,CRB_CH1,/*Sec*/ //,CRB_CH1/*Pri*/,CRB_CH1 /*Sec*/,
                       
                        CRA_CH2/*Pri*/,CRA_CH2 /*Sec*/,CRA_CH1/*Pri*/,CRA_CH1, /*Sec*/ //,CRA_CH2/*Pri*/,CRA_CH2 /*Sec*/,
                   
                        0,
                        0,
                        0,
                        0
                   
     };

How do you see that these devices actually fail?

When I change the control word for the control register F (CRF) from common mode of work to analog loop back , compile and load , the funcionality of my code doesn't change.

This is just one example of how the funcionality of the codecs doesn't change

thanks for your support

Regards ,

Alon

Hi Alon

Apologies for the delay.

Your configuration appears simple. It looks like clock and framesync for both transmitter and receiver are fed externally. 

Have you had chance to explore other debugging tips I mentioned earlier? Probing and reading back written-data might throw something.

Regards

Prasanth.