We have designed a circuit for the ADSP-BF523BBCZ-5A but we have fitted ADSP-BF527BBCZ-5A because the 523 part was not available. In theory the 527 can go in place of the 523 because I have left the USB pins floating and we are not using the MAC controller. The input clock is 25.6MHz, the core is setup for 512MHz and the external SDRAM clock is 128MHz.
At room temperature, up to roughly 75DegC the DSP boots up and operates as expected.
1) At about 80DegC+ the DSP does not boot up. When there is a bad-boot, the SPI clock is about x3.7 slower than required so at turn on the SPI accesses take longer since the clock is slower. The number of SPI accesses appears to match a good-boot so the DSP is getting all of the application code from external memory.
This implies the DSP is executing the right boot sequence.
2) When there is a bad-boot, the SDRAM clock is ~34MHz and remains 34MHz all the time.
This implies the PLL has started wrong and does not correct itself.
The UART comms rate is wrong and we cannot communicate with the board.
3) Applying an soft reset (via RESET) or power cycling the board quickly makes the DSP boot up correctly. A quick power cycle would have left residual charge/voltage on the board.
4) Removing the power for about 15 seconds and then applying power results in a bad-boot.
Conclusion of 3) and 4) implies a soft reset is required for the DSP to have a good-boot if there was a bad-boot.
- The power rails are within spec when the DSP reset is released. 3V3 = 3.33V, 2V5 = 2.47V and 1V2 = 1.17V.
- The input clock (25.6MHz) is stable when the DSP reset is released.
- Pin L19 (VPPOTP) is connected to 1V2, it should be connected to 2V5. I will fix this when the board is re-spun. We are not using the security features or the OTP memory plus the board boots successfully up to 75DegC so I can’t see how this mistake will explain the problem.
- Is there temperature compensation in the PLL?
- What can cause the PLL to start wrong?
- Do we need to setup USB and MAC registers in the 527 to ensure these peripherals are not enabled?
- What is the PLL powered from, VDDINT?
VPPOTP is 1V2 right now. It will be 2V5 when the board is re-spun.