I have read the BF548 hardware reference guide, and am a little confused by what it says regarding byte access to the USB FIFOs through the MMR peripheral bus (not DMA).
ADSP-BF54x Blackfin Processor
(includes ADSP-BF542, ADSP-BF544,
ADSP-BF547, ADSP-BF548, ADSP-BF549)
Revision 1.0, August 2010
For endpoint zero, I assume that the same mechanism as used for other TX endpoints applies - that is, I can use the USB_TXCOUNT register, load it with an odd number, and then perform word writes to USB_EP0_FIFO (0xFFC03C80). If I need to write say 5 bytes, I should set USB_TXCOUNT to 5, then
perform 3 word writes, and the last word write will only result in one byte being written to the fifo. Is this correct?
The part I find confusing is on page 26-130, with regards to USB_TXCOUNT register:
"The value is decremented
by two when the processor core writes to the corresponding USB_EPx_FIFO
high word address and is decremented by one when the processor core
writes a byte to the FIFO using the corresponding USB_EPx_FIFO low word
address. If the count itself reaches 0x0001 (which would only happen for
odd-sized transfers), the next write into either USB_EPx_FIFO high word or
USB_EPx_FIFO low word writes only the least significant byte of the half
word into the FIFO. This aids DMA transfers that require IO accesses to
go to the same address. "
The datasheet is unclear about what address exactly is the "high word" address and what address is the "low word" address. I assume that 0xFFC03C80 is the high word address and that this should be used when programming DMA transfers. Is this correct?
Is the "low word" address at the high word address + 4, as hinted at on page 26-88:
For EP0 RX transfers, if the last packet is not a multiple of four
bytes it is strongly recommended that the remainder (n bytes mod
4) be unloaded from the FIFO using a special byte addressing
FIFO register (EP0 FIFO address + 4).