Blackfin Bootup Issue?

We have been building products with the Blackfin ADSP-BF537 (and earlier products with the ADSP-BF533).  We boot from external flash, use primarily the Eval Board core as the schematic with the ADM708 reset IC and have two Linear Technology LTM8023 modules that convert the DC input voltage (typically 10-28VDC) to 3.3V and 1.3V for the core.  Sometimes we get a report that when power is turned on to the unit it does boot up and recycling power remedies this.  The problem is VERY infrequent.  For example, in one application where there are 80 units in the field it may happen one time in a week and on a different unit each time.

Our units are typically used as on-board audio players in amusement park mobile vehicles.  On one application where the problem occurred more prevalently, we found that customer's power supply was crowbarring at startup creating an very undesirable input voltage waveform at startup.  Changing to a more robust supply fixed the issue however, on this an other instance we still see the infrequent problem.

Does anyone have any similar experience with this type of issue and have any solutions to offer?

Parents
  • 0
    •  Analog Employees 
    on Feb 15, 2012 11:22 PM over 8 years ago

    Hi Rick.

    First, you mentioned your schematics were confidential, so I saved them off and deleted them from this thread (instead copying your text below so that other forum readers can still see the full discussion).

    On to a response here - there are too many variables with process, temperature, and voltage to define an exact relationship between the VDDEXT ramp and the VDDINT ramp where this anomaly becomes problematic, so if that's what you are asking, I'm afraid I cannot provide further details beyond what we've described in the thread above and in the anomaly sheet. However, if you are asking how soon after VDDEXT is above the minimum spec that you can begin ramping up VDDINT, then the answer is "immediately".  As long as VDDEXT is above the minimum spec before VDDINT starts coming up, there is NO RISK for this anomaly.  Tailoring the response to what you're working with, according to an earlier post, you are using the commercial grade 600 MHz BF537. So, once your VDDEXT is above the minimum spec of 2.25 V, you can safely begin ramping VDDINT because you've now met the only criteria for avoiding this anomaly.  That said, it looks to me like your idea of using the PGOOD coming from the 3.3V LTM8023 to trigger the 1.3V supply will work great.  The PGOOD should only go high when the ADJ pin is within 10% of the programmed Vout, so it'll trigger at ~3V, which is well after crossing the critical threshold of 2.25 V.

    Please let us know if you have further questions/concerns.

    -Joe

    ---INCLUDE RICK'S PREVIOUS POST---

    Dear Joe

    The rPOD-8.4 is the newer product and one that we are trying to revise

    for many reasons.  We want to include any fixes that make it more

    reliable.  The rPOD-10.2 is our discontinued product and we only have

    one left to test.  We could not make the problem happen here on either

    product with the exception of an older 10.2 version that would not come

    up consistently (much more than being reported, but still very

    infrequently so I am not sure if this is indicative however, it is the

    one we took the scope pix from).  When that unit did not boot on power

    up, a reset did work.

    I am attaching confidential schematics of both designs before our

    revisions that we are working on.  Our thought now is to have the PM2

    3.3V LTM8023 module's PGOOD pin trigger the PM3 1.3V regulator.  There

    is even a soft start feature for this control pin.  There must be some

    minimum time required (and it appears you are saying there is no

    maximum) for 1.3V to come up after the 3.3V to avoid the race

    condition.  That is one of the numbers I am looking for.

    We are using a 27MHz clock for the BF537 and the ADM708 (used in your

    eval board).  It has a 200ms reset time and that should be enough.

    Thanks for your input.

    Sincerely,

    Rick Simon, CFO

    Simon-Kaloi Engineering, Ltd.

    31192 La Baya Drive Unit G

    Westlake Village, CA 91362

    Phone: (818) 707-8400

    Fax: (818) 707-8401

    email: rick@skeng.com

    website: http://www.skeng.com

Reply
  • 0
    •  Analog Employees 
    on Feb 15, 2012 11:22 PM over 8 years ago

    Hi Rick.

    First, you mentioned your schematics were confidential, so I saved them off and deleted them from this thread (instead copying your text below so that other forum readers can still see the full discussion).

    On to a response here - there are too many variables with process, temperature, and voltage to define an exact relationship between the VDDEXT ramp and the VDDINT ramp where this anomaly becomes problematic, so if that's what you are asking, I'm afraid I cannot provide further details beyond what we've described in the thread above and in the anomaly sheet. However, if you are asking how soon after VDDEXT is above the minimum spec that you can begin ramping up VDDINT, then the answer is "immediately".  As long as VDDEXT is above the minimum spec before VDDINT starts coming up, there is NO RISK for this anomaly.  Tailoring the response to what you're working with, according to an earlier post, you are using the commercial grade 600 MHz BF537. So, once your VDDEXT is above the minimum spec of 2.25 V, you can safely begin ramping VDDINT because you've now met the only criteria for avoiding this anomaly.  That said, it looks to me like your idea of using the PGOOD coming from the 3.3V LTM8023 to trigger the 1.3V supply will work great.  The PGOOD should only go high when the ADJ pin is within 10% of the programmed Vout, so it'll trigger at ~3V, which is well after crossing the critical threshold of 2.25 V.

    Please let us know if you have further questions/concerns.

    -Joe

    ---INCLUDE RICK'S PREVIOUS POST---

    Dear Joe

    The rPOD-8.4 is the newer product and one that we are trying to revise

    for many reasons.  We want to include any fixes that make it more

    reliable.  The rPOD-10.2 is our discontinued product and we only have

    one left to test.  We could not make the problem happen here on either

    product with the exception of an older 10.2 version that would not come

    up consistently (much more than being reported, but still very

    infrequently so I am not sure if this is indicative however, it is the

    one we took the scope pix from).  When that unit did not boot on power

    up, a reset did work.

    I am attaching confidential schematics of both designs before our

    revisions that we are working on.  Our thought now is to have the PM2

    3.3V LTM8023 module's PGOOD pin trigger the PM3 1.3V regulator.  There

    is even a soft start feature for this control pin.  There must be some

    minimum time required (and it appears you are saying there is no

    maximum) for 1.3V to come up after the 3.3V to avoid the race

    condition.  That is one of the numbers I am looking for.

    We are using a 27MHz clock for the BF537 and the ADM708 (used in your

    eval board).  It has a 200ms reset time and that should be enough.

    Thanks for your input.

    Sincerely,

    Rick Simon, CFO

    Simon-Kaloi Engineering, Ltd.

    31192 La Baya Drive Unit G

    Westlake Village, CA 91362

    Phone: (818) 707-8400

    Fax: (818) 707-8401

    email: rick@skeng.com

    website: http://www.skeng.com

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