Blackfin Bootup Issue?

We have been building products with the Blackfin ADSP-BF537 (and earlier products with the ADSP-BF533).  We boot from external flash, use primarily the Eval Board core as the schematic with the ADM708 reset IC and have two Linear Technology LTM8023 modules that convert the DC input voltage (typically 10-28VDC) to 3.3V and 1.3V for the core.  Sometimes we get a report that when power is turned on to the unit it does boot up and recycling power remedies this.  The problem is VERY infrequent.  For example, in one application where there are 80 units in the field it may happen one time in a week and on a different unit each time.

Our units are typically used as on-board audio players in amusement park mobile vehicles.  On one application where the problem occurred more prevalently, we found that customer's power supply was crowbarring at startup creating an very undesirable input voltage waveform at startup.  Changing to a more robust supply fixed the issue however, on this an other instance we still see the infrequent problem.

Does anyone have any similar experience with this type of issue and have any solutions to offer?

  • 0
    •  Analog Employees 
    on Feb 13, 2012 1:20 AM

    Hi Rick,

    If VDDINT is powered up before VDDEXT, then PLL may latch incorrect SSEL and CSEL resulting in boot failure. Can you please take a look at anomaly 05000489 - PLL May Latch Incorrect Values Coming Out of Reset in the below link:



    Best Regards,




  • Dear Guru,

    We went away from the on-chip regulator (with the external components)

    and used a separate regulator for the core VDDINT because the datasheet

    said you could and it cleared route space for our complex boards some

    that have two processors.  We hear from our customer that even versions

    of our product that use the on-chip regulator occasionally exhibit this

    problem as well as ones with the external regulator.

    I am attaching two images for you to look at.  In both case the orange

    is the 24VDC input supply, the cyan is the 3.3V regulated supply and the

    purple is the 1.3V supply.

    The rPOD-10.2 uses the on-chip regulator.  The rPOD-8.4 uses the

    external.  Even though the power up sequences are slightly different, it

    looks like even with on-chip regulation the 1.2V stabilizes before the

    3.3V stabilizes.  Perhaps this is why we see the issue on both units.

    Here are some questions:

    1. We have been purchasing the ADSP-BF537KBCZ-6B1 or -6BX or -6BV  and

    Rev 0.3 is the latest revision we have purchased.  Are there later

    revisions of this part e.g., 0.4 available that do not have this issue?

    2. Can any pin on the processor such as VROUT0 or VROUT1 be used as

    delayed control logic signal to turn on our 1.2V ext regulator after a


    3. We use the ADM708 (with 200msec delay) for our reset IC.  If we let

    the 3.3V come up as it does now, then let the reset release the 1.2V

    regulator (that will be held off at startup) is that too long of a delay

    for VDDINT?

    4. What is the maximum delay you can use to bring up the VDDINT?

    Thanks for your help.


    Rick Simon, CFO

    Simon-Kaloi Engineering, Ltd.

    31192 La Baya Drive Unit G

    Westlake Village, CA 91362

    Phone: (818) 707-8400

    Fax: (818) 707-8401



  • Some more questions and correction.  All of my references to 1.2V should

    be 1.3V.

    If we are to delay the startup of the 1.2V regulator, what is the safe

    range for the timing between the two.  Also, can they be in sync and

    come up at the same time?


  • 0
    •  Analog Employees 
    on Feb 14, 2012 1:47 AM

    Hi Rick,

    Using the on-chip regulator is one of the workaround for this anomaly. If you are seeing this problem on platforms that uses on-chip regulator, then this anomaly may not be the cause of the issue.

    0.3 rev is the latest silicon rev for BF537.

    When you bring VDDEXT first, VDDINT can be brought up once VDDEXT reaches to its minimum value (spec in datasheet). I'll get back to you regarding Q2 and Q4