BF527&AD73311L

Hello,

before writing into SPORT transmit Buffer, you should check whether that SPORT Transmit buffer is empty or not. Should not keep on writing into it.

Did you probed the transmit data pin (DTPRI) of the SPORT. Whether you see expected SPORT bit sequence there? I am sure it is not.

As shown in SPORT block diagram, data paths are 16- or 32-bits wide, depending on  SLEN. for SLEN = 2 to 15, a 16-bit data path with 8-deep fifo is used. for SLEN = 16 to 31, a 32-bit data path with 4-deep fifo is used.

With your code, the SPORT Transmit buffer will get overwritten before transmitting.

To check whether SPORT transmit buffer is empty or not, poll TXHRE bit of the SPORT_STAT register.

I rewrote the code. But result not changed.

My code version 1:

s16_t buf_cfg[] = { 0x910F, 0x890F, 0x810F, 0x9279, 0x9279, 0x8A79, 0x8279, 0x9520, 0x9520, 0x8D20, 0x8520, 0x9021, 0x9021, 0x8821, 0x8031, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF };    

    u8_t i = 0;

    while (i<19)

    {

        if (*pSPORT0_STAT & (1 << 6)) // get state TXHRE bit

        {

            *pSPORT0_TX16 = buf_cfg[i];

            i++;

        }       

    }

My code version 2:

s16_t buf_cfg[] = { 0x910F, 0x890F, 0x810F, 0x9279, 0x9279, 0x8A79, 0x8279, 0x9520, 0x9520, 0x8D20, 0x8520, 0x9021, 0x9021, 0x8821, 0x8031, 0x7FFF, 0x7FFF, 0x7FFF, 0x7FFF };    

    u8_t i = 0;

    while (i<19)

    {

        if (!(*pSPORT0_STAT & (1 << 3))) // get state TXF bit

        {

            *pSPORT0_TX16 = buf_cfg[i];

            i++;

        }       

    }

Hi,

The code looks correct. Try to confirm whether Blackfin is sending data (/command) as expected, by probing the SPORT signals. You may need to refer datasheet of other device to check what is it's timing and whether SPORT is configured accordingly.

If Blackfin SPORT is not sending data as expected, let me know the details.

it is working:

// reset codecs

    *pPORTFIO_SET = PF_NRST_CDC    ;

    *pPORTFIO_SET = PF_CS_SPORT;        

    *pPORTFIO_CLEAR = PF_NRST_CDC    ;

    system_wait(100);

    *pPORTFIO_SET = PF_NRST_CDC    ;

    system_wait(1000);       

    // SPORT0

    *pSPORT0_TCR1 = TFSR;

    *pSPORT0_TCR2 = AD73311_DATALEN - 1;

    *pSPORT0_RCR1 = RFSR;

    *pSPORT0_RCR2 = AD73311_DATALEN - 1;

    // enable Sport0 TX and RX

    *pSPORT0_TCR1     = (*pSPORT0_TCR1 | TSPEN /*| DITFS*/);

    *pSPORT0_RCR1     = (*pSPORT0_RCR1 | RSPEN);              

    *pSPORT0_TX16 = 0x910F; // B      

    *pSPORT0_TX16 = 0x890F; // B

    *pSPORT0_TX16 = 0x810F; // B

    u16_t tmp = *pSPORT0_RX16;  // read answer from codecs

    tmp = *pSPORT0_RX16;

    tmp = *pSPORT0_RX16;

    while (0x00 == (0x40 & *pSPORT0_STAT));

    *pSPORT0_TX16 = 0x9279; // C       

    *pSPORT0_TX16 = 0x8A79; // C       

    *pSPORT0_TX16 = 0x8279; // C   

    //*pSPORT0_TX16 = 0x9300; // D   

    //*pSPORT0_TX16 = 0x8B00; // D   

    //*pSPORT0_TX16 = 0x8300; // D

    //*pSPORT0_TX16 = 0x8420; // E

    //*pSPORT0_TX16 = 0x8420; // E   

    tmp = *pSPORT0_RX16;

    tmp = *pSPORT0_RX16;

    tmp = *pSPORT0_RX16;

    *pSPORT0_TX16 = 0x9500; // F

    *pSPORT0_TX16 = 0x8D20; // F   

    *pSPORT0_TX16 = 0x8520; // F      

    tmp = *pSPORT0_RX16;

    tmp = *pSPORT0_RX16;

    tmp = *pSPORT0_RX16;   

    *pSPORT0_TX16 = 0x9021; // A    

    *pSPORT0_TX16 = 0x8821; // A    

    *pSPORT0_TX16 = 0x8021; // A