Interfacing to AD7927

I interfaced a Blackfin to the AD7927, the AD7927 says it is SPI compatible which is good as I only had a SPI port left to use but the timing in the AD7927 datasheet (fig 26 on page 22, it appears to sample DIN and change DOUT on falling edge) appears to be a little off from normal SPI when compared to the SPI timing diagram for the Blackfin (Figs 13-6 and 7 on page 13-13 in the ADSP-BF59X Hardware Reference where MOSI and MISO both sample or change on the same edge). I've got them tied together on my board and have the AD7927 set to sequence all 8 channels and the AD7927 seems to be doing that but the data read by the Blackfin appears inconsistent (have CPOL=1 and CPHA=0 in SPI1 config register). Is there an example of the best settings to use or should I change settings after setting up the AD7927 to better align the DOUT data for the Blackfin?

  • 0
    •  Analog Employees 
    on Oct 10, 2012 11:20 AM

    Hi Frank,

    The way I see these timings is (for read operation), since ADC is driving data on falling edge of ADC_CLK which is generated by Host and same clock is used by Host to sample the data, so sampling bits on the same edge as driving edge of ADC should not cause any problem. I guess it is not possible for ADC to drive new bit on the exact incoming driving edge with 0nsec delay.

    This approach (against the traditional approach of using driving and sampling edge opposite) ensures that reliable ADC operation even at maximum speed, enabling a full cycle timing on the receive direction.

  • Hi Prashant,

    Well, the only way I can get this to work reliably is to change CPHA modes between reading and writing. I don't know if it is the Blackfin or the ADC but I cannot reliably read and write using only one mode. While both devices sample on a clock "edge" I cannot determine if the devices are truly edge triggered (i.e. a flip-flop sampling the pin) or using a transparent latch internally to sample the pin. In any case I solved the issue with mode changing, not the best solution but has been 100% reliable.

    I do have one final question:

    As CPHA=1 requires s/w control of the SPISEL pin is there any issues to letting the s/w control happen even with CPHA = 0?

  • 0
    •  Analog Employees 
    on Oct 11, 2012 5:55 AM

    Hi Frank,

     

    As you know when CPHA=0, SPI slave select lines will be exclusively controlled by SPI hardware. So, trying to do software control by manipulating FLGx bits of SPI_FLG register when CPHA=0, will not work.

    As mentioned in HRM, "If CPHA = 0, the SPI hardware sets the output value and the FLGx bits are ignored".

     

    However, Slave select lines can be controlled in software when CPHA=0. The corresponding SSEL pin should be configured as GP output (FERx=0), so it's like GP output pin controlling using DATA_SET and DATA_CLR registers. (This is the way Boot ROM boots from SPI memory in CPHA=CPOL=1 mode).

    But have to make sure that GP output should not be toggled when SPI transfer is on-going.

  • Hi Frank,

    I have this exact problem with the AVR32.  I've been pulling my hair out because there is no standard SPI mode that works for the 7927 for both reading and writing.  I'm curious how you got the mode switching to work.  Since SPI reads and writes at the same time, how are you able to change modes between? 

    thanks,

    Darren

  • 0
    •  Analog Employees 
    on Jan 29, 2013 9:07 AM

    Hi Darren,

    You would likely be best asking this question over in the Data Converters community, as you are using an AVR32 as your processor. They should be able to advise how to use the AD7927 in the setup you describe above.

    Regards,

    Craig.