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Interfacing to AD7927

I interfaced a Blackfin to the AD7927, the AD7927 says it is SPI compatible which is good as I only had a SPI port left to use but the timing in the AD7927 datasheet (fig 26 on page 22, it appears to sample DIN and change DOUT on falling edge) appears to be a little off from normal SPI when compared to the SPI timing diagram for the Blackfin (Figs 13-6 and 7 on page 13-13 in the ADSP-BF59X Hardware Reference where MOSI and MISO both sample or change on the same edge). I've got them tied together on my board and have the AD7927 set to sequence all 8 channels and the AD7927 seems to be doing that but the data read by the Blackfin appears inconsistent (have CPOL=1 and CPHA=0 in SPI1 config register). Is there an example of the best settings to use or should I change settings after setting up the AD7927 to better align the DOUT data for the Blackfin?

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  • Hi Frank,

     

    As you know when CPHA=0, SPI slave select lines will be exclusively controlled by SPI hardware. So, trying to do software control by manipulating FLGx bits of SPI_FLG register when CPHA=0, will not work.

    As mentioned in HRM, "If CPHA = 0, the SPI hardware sets the output value and the FLGx bits are ignored".

     

    However, Slave select lines can be controlled in software when CPHA=0. The corresponding SSEL pin should be configured as GP output (FERx=0), so it's like GP output pin controlling using DATA_SET and DATA_CLR registers. (This is the way Boot ROM boots from SPI memory in CPHA=CPOL=1 mode).

    But have to make sure that GP output should not be toggled when SPI transfer is on-going.

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  • Hi Frank,

     

    As you know when CPHA=0, SPI slave select lines will be exclusively controlled by SPI hardware. So, trying to do software control by manipulating FLGx bits of SPI_FLG register when CPHA=0, will not work.

    As mentioned in HRM, "If CPHA = 0, the SPI hardware sets the output value and the FLGx bits are ignored".

     

    However, Slave select lines can be controlled in software when CPHA=0. The corresponding SSEL pin should be configured as GP output (FERx=0), so it's like GP output pin controlling using DATA_SET and DATA_CLR registers. (This is the way Boot ROM boots from SPI memory in CPHA=CPOL=1 mode).

    But have to make sure that GP output should not be toggled when SPI transfer is on-going.

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