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Interfacing to AD7927

I interfaced a Blackfin to the AD7927, the AD7927 says it is SPI compatible which is good as I only had a SPI port left to use but the timing in the AD7927 datasheet (fig 26 on page 22, it appears to sample DIN and change DOUT on falling edge) appears to be a little off from normal SPI when compared to the SPI timing diagram for the Blackfin (Figs 13-6 and 7 on page 13-13 in the ADSP-BF59X Hardware Reference where MOSI and MISO both sample or change on the same edge). I've got them tied together on my board and have the AD7927 set to sequence all 8 channels and the AD7927 seems to be doing that but the data read by the Blackfin appears inconsistent (have CPOL=1 and CPHA=0 in SPI1 config register). Is there an example of the best settings to use or should I change settings after setting up the AD7927 to better align the DOUT data for the Blackfin?

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  • Hi Frank,

    The way I see these timings is (for read operation), since ADC is driving data on falling edge of ADC_CLK which is generated by Host and same clock is used by Host to sample the data, so sampling bits on the same edge as driving edge of ADC should not cause any problem. I guess it is not possible for ADC to drive new bit on the exact incoming driving edge with 0nsec delay.

    This approach (against the traditional approach of using driving and sampling edge opposite) ensures that reliable ADC operation even at maximum speed, enabling a full cycle timing on the receive direction.

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  • Hi Frank,

    The way I see these timings is (for read operation), since ADC is driving data on falling edge of ADC_CLK which is generated by Host and same clock is used by Host to sample the data, so sampling bits on the same edge as driving edge of ADC should not cause any problem. I guess it is not possible for ADC to drive new bit on the exact incoming driving edge with 0nsec delay.

    This approach (against the traditional approach of using driving and sampling edge opposite) ensures that reliable ADC operation even at maximum speed, enabling a full cycle timing on the receive direction.

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