Interfacing to AD7927

I interfaced a Blackfin to the AD7927, the AD7927 says it is SPI compatible which is good as I only had a SPI port left to use but the timing in the AD7927 datasheet (fig 26 on page 22, it appears to sample DIN and change DOUT on falling edge) appears to be a little off from normal SPI when compared to the SPI timing diagram for the Blackfin (Figs 13-6 and 7 on page 13-13 in the ADSP-BF59X Hardware Reference where MOSI and MISO both sample or change on the same edge). I've got them tied together on my board and have the AD7927 set to sequence all 8 channels and the AD7927 seems to be doing that but the data read by the Blackfin appears inconsistent (have CPOL=1 and CPHA=0 in SPI1 config register). Is there an example of the best settings to use or should I change settings after setting up the AD7927 to better align the DOUT data for the Blackfin?

  • 0
    •  Analog Employees 
    on Oct 3, 2012 3:57 PM

    Hi FrankT

    Have you tried a setting of CPOL =1, CPHA=1 ?

    Also you mentioned " I've got them tied together on my board". Could you clarify this? Ideally if you can send a shot of the schematic showing the wiring between the Blackfin and the AD7927 that would be great.



  • Tried with CPOL = 1 and CPHA = 1 and data reading works properly now but it fails to write properly to the AD7927 to set config register in it. It seems I will need to set up the AD7927 with CPHA = 0 then change to CPHA = 1 to read which is a pain but I may be able to make that work. So two questions:

    1. As CPHA=1 requires s/w control of the SPISEL pin is there any issues to letting the s/w control happen even with CPHA = 0? Basically can I have one routine that executes a transfer or will I need two different ones, one for CPHA=0 and another for CPHA=1?

    2. Can you find who at ADI wrote in nice bold letters "High speed serial interface SPI-, QSPITm-, MICROWIRETm-, DSP-compatible" on the front of the AD7927 datasheet and explain to them it is NOT SPI compatible, at least as far as using it with a Blackfin is concerned?

    To answer your questions, the schematic is across multiple pages so not so easy to post a single image. I'm using SPI1 so I have SPI1_MOSI connected to DIN, SPI1_MISO connected to DOUT, SPI1_SCK connected to SCLK and /SPI1_SSEL5 connected to /CS. I can see the half-clock difference between DIN and DOUT in a logic analyzer

  • 0
    •  Analog Employees 
    on Oct 5, 2012 11:33 AM

    Hi FrankT

    I have referrered you question to the DSP group and will let you know their responce shortly.



  • 0
    •  Analog Employees 
    on Oct 8, 2012 10:42 AM

    Hi Frank,

    Sorry for jumping here, but I think CPHA=0 and CPOL=1 is the correct setting for Blackfin to read the data from AD7927. Not sure what inconsistent behaviour do you see.

    What is the SCLK rate in your application?

    Are you making sure that tQUITE parameter of AD7929 is satisfied?

    If CPHA=0, then tQUITE value provided to ADC would be half of SPI_CLOCK period.

    Can you try ADC reads at 10MHz or below?

  • Hi Prashant,

    To answer your questions:
    1. Blackfin SCLK is 100MHz, CCLK is 400MHz
    2. tQUIET is satisfied, overall sample rate is about 1KHz
    3. Currently reading ADC at 1MHz

    Problem is that the SPI format of the Blackfin is not the same as that for the AD7927, Below are the timing diagrams from both data sheets. On the Blackfin it expects that MOSI and MISO change on the same clock edge and are both sampled on the opposing clock edge. As can bee seen in the below diagram, MOSI and MISO always change together and are sampled together no matter the format.

    The AD7927 however changes DOUT on falling edge and samples DIN also on the falling edge (it basically expects DIN to change on rising edge), this does not match the timing for the Blackfin where it would expect both DIN and DOUT to change on the same edge.Reading the descriptions of timing parameters t4, t9 and t10 for the AD7927 state:

    t4: Data access time after SCLK falling edge
    t9: DIN setup time prior to SCLK falling edge
    t10: DIN hold time after SCLK falling edge

    which tells me that it expects to sample DIN on the falling edge and change DOUT on the same falling edge, no SPI format in the Blackfin meets that timing that I can see.