CLDP Reprorted done but code is not executing from spi flash when change Boot Mode 3 to Spimaster and pressed reset.

Hi,

 We have anomaly that SPI Master Boot Fails When Block Payload Size Exceeds 65,532 Bytes. Can you please check if you are hitting this anomaly ?

 When booting in SPI Master Mode, the boot ROM configures the SPI in 8-bit mode and uses the SPI Receive Counter register (SPI_RWC) to store the payload byte count. By definition, this 16-bit register can only accommodate payload sizes up to 64KB. When the boot code transfers a payload greater than this, it is supposed to break the data into blocks of 64KB each by writing the SPI_RWC register to 64K, but it erroneously sets the count to 0 instead. When this occurs, the SPI port halts and the boot process stops.

To overcome this, use the -MaxBlockSize switch to limit the block size to a value less than 64K. As boot code needs to be aligned on a 32-bit boundary, the maximum size of any individual block is 65,532 (0xFFFC); therefore, if your loader file exceeds 64KB, then use -MaxBlockSize 0xFFFC in the additional options while creating the loader file.

Please refer "16000047" in the below linked anomaly sheet:

https://www.analog.com/media/en/dsp-documentation/integrated-circuit-anomalies/ADSP-BF60x-anomaly.pdf

 If you are not hitting the above anomaly, then Please try to connect the processor in DND(Do Not Disturb) mode and check. This would help to isolate whether the issue is with booting or the application. Please refer the below FAQ for connecting the processor in DND mode.

https://ez.analog.com/dsp/software-and-development-tools/hardware-tools/w/documents/6749/faq-how-to-debug-a-target-board-which-boots-from-flash-using-crosscore-embedded-studio

 Also please try by changing the erase affected as erase all and let us know the response.

Regards,

Divya.P

Hi,

 We have anomaly that SPI Master Boot Fails When Block Payload Size Exceeds 65,532 Bytes. Can you please check if you are hitting this anomaly ?

 When booting in SPI Master Mode, the boot ROM configures the SPI in 8-bit mode and uses the SPI Receive Counter register (SPI_RWC) to store the payload byte count. By definition, this 16-bit register can only accommodate payload sizes up to 64KB. When the boot code transfers a payload greater than this, it is supposed to break the data into blocks of 64KB each by writing the SPI_RWC register to 64K, but it erroneously sets the count to 0 instead. When this occurs, the SPI port halts and the boot process stops.

To overcome this, use the -MaxBlockSize switch to limit the block size to a value less than 64K. As boot code needs to be aligned on a 32-bit boundary, the maximum size of any individual block is 65,532 (0xFFFC); therefore, if your loader file exceeds 64KB, then use -MaxBlockSize 0xFFFC in the additional options while creating the loader file.

Please refer "16000047" in the below linked anomaly sheet:

https://www.analog.com/media/en/dsp-documentation/integrated-circuit-anomalies/ADSP-BF60x-anomaly.pdf

 If you are not hitting the above anomaly, then Please try to connect the processor in DND(Do Not Disturb) mode and check. This would help to isolate whether the issue is with booting or the application. Please refer the below FAQ for connecting the processor in DND mode.

https://ez.analog.com/dsp/software-and-development-tools/hardware-tools/w/documents/6749/faq-how-to-debug-a-target-board-which-boots-from-flash-using-crosscore-embedded-studio

 Also please try by changing the erase affected as erase all and let us know the response.

Regards,

Divya.P

Hi,

Thanks for the support it is working now,I have followed anomaly 16000047 for ADSP-BF609 and done booting from spi flash