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Please help to estimate resources of ADSP-BF592

There is a very simple task:

1. Read data (Si1, Si2) from dual channel ADC (AD9248) 14bit, 10 MHz, parallel data interface. Data are read with use of multiplexing ADC channels то PPI.

2. Sum rezults: E1+=Si1, E2+=Si2, i++.

3. If i>N send E1,E2 to UART or SPI, and E1=0, E2=0, i=0. (N=65536).

What problems can arise in case of implementation of this task on ADSP-BF592?

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  • Hi,

    The Multiplexed Data Format timing diagram suggests to connect MUX_SELECT pin to CLK signals (CLK_A = CLK_B =MUX_SELECT), which means that ADC drives data from each ADC in single clock cycle. Therefore Host should sample data bus on both edges of CLK, which is not possible when PPI is used to interface to such timings. PPI will sample the data bus only on active edges of PPI_CLK (rising or falling) based on POLC bit setting.

    So, if you connect CLK_A = CLK_B =MUX_SELECT, PPI will give you data from single ADC based on whether sampling edge is rising edge or falling edge.

    I am not sure if it is OK to connect another signal to MUX_SELECT which has half the freq of CLK signal. If yes, this will ensure that ADC data bus toggled at PPI_CLK rate. (but note that, datasheet mentions that 'Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade AC performance'.

    This PPI_CLK and MUX_SELECT signals you can generate using GP Timers of BF592 processor. Enable these timers at same instance (using single instruction). This will ensure that PPI_CLK and MUX_SELECT signals would be almost synchronous.

    Hope it helps. Let me know if you need more clarifications at the processor end. For AD9248 related queries, you can contact http://ez.analog.com/community/data_converters/high-speed_adcs community

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  • Hi,

    The Multiplexed Data Format timing diagram suggests to connect MUX_SELECT pin to CLK signals (CLK_A = CLK_B =MUX_SELECT), which means that ADC drives data from each ADC in single clock cycle. Therefore Host should sample data bus on both edges of CLK, which is not possible when PPI is used to interface to such timings. PPI will sample the data bus only on active edges of PPI_CLK (rising or falling) based on POLC bit setting.

    So, if you connect CLK_A = CLK_B =MUX_SELECT, PPI will give you data from single ADC based on whether sampling edge is rising edge or falling edge.

    I am not sure if it is OK to connect another signal to MUX_SELECT which has half the freq of CLK signal. If yes, this will ensure that ADC data bus toggled at PPI_CLK rate. (but note that, datasheet mentions that 'Any skew between CLK_A, CLK_B, and MUX_SELECT can degrade AC performance'.

    This PPI_CLK and MUX_SELECT signals you can generate using GP Timers of BF592 processor. Enable these timers at same instance (using single instruction). This will ensure that PPI_CLK and MUX_SELECT signals would be almost synchronous.

    Hope it helps. Let me know if you need more clarifications at the processor end. For AD9248 related queries, you can contact http://ez.analog.com/community/data_converters/high-speed_adcs community

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