Post Go back to editing

The SPI Master Mode Boot from SPI Memory


    When I use the bf537, and I set the bf537 boot from SPI . There is an question that confuse me.

    When I refer the bf537 datasheet, the datasheet says as follow :

For SPI master mode boot (BMODE = 011), the boot kernel assumes that the

SPI baud rate is SCLK/(2 x 133) Kbit/s. SPI serial EEPROMs that are

8-bit, 16-bit, and 24-bit addressable are supported. The SPI uses the PF10

output pin to select a single SPI EEPROM device. The SPI controller

submits successive read commands at addresses 0x00, 0x0000, and

0x000000 until a valid 8-, 16-, or 24-bit addressable EEPROM is

detected. It then begins clocking data into the beginning of L1 instruction


there is a centence that I marked with red color, say the PF10 is uesd to select the EEPROM device.

So can someone tell me ,  can I use other pin (for example PF5)  to select the EEPROM? And how to do it?

Second. is that  each processor  use a fixed pin to select the EEPROM when boot from SPI , and can not change?

thank you very much!!

  • Hi,

    this is a hard coded implementation and cannot be changed. PF10 is the slave select pin #1 for the SPI interface anyway. The pin has no other peripheral function as you can see in the HRM. A slave select pin is mandatory so why do you need to change it?

    Later Blackfin processors  like ADSP-BF52x/54x/51x/50x/59x/60x have an API for the Boot ROM to manipulate settings like that.

  • Thank you vrey much!!!!  I do not want to change the pin PF10, I just think about to boot from SPI  with to 2  application.  If  there is 2 or more pin can be use to select the device,  I just want to try to make the board to boot from SPI and with  several  application.

    but as you say.  I will not make mistake  again.  

    you really help me a lot!!!