I would like to understand how the (BF) SPORT interface handles the clocks when started for the first time. In my application, the SPORT interface is configured to run in "multi-channel" mode with external frame-sync and bit-clock. The configuration steps are as follows:
1. Keep the clocks quiet (idle).
2. Configure SPORT.
3. Configure the DMA.
4. Start SPORT RX, then TX.
5. Start frame-sync and bit-clock.
What I see is that the SPORT transmits the first data word is only on the second frame-sync period (I this case it's all zeros). On the first frame sync the data line seems to be undefined (random).
(1) - frame sync (96 kHz)
(2) - bit clock (12.288 MHz)
(3) - data
Here is a zoom on the first frame sync:
I though that this is due to the fact that the FS and bit-clock signal start exactly at the same time and that the SPORT has no time to sample the first rising edge of the FS signal. So I have tried starting the bit-clock one cycle before starting the frame-sync signal but it didn't help. The SPORT still sends the first valid word on the second frame-sync.
I didn't find any explanation about the clock requirements in the specification. Is there a way to configure the clock signal so that the SPORT starts sending the first data word in the first frame-sync?