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# Limit Duty Cycle in SC589 with respect to the input ADC data

Hi Team,

As per my understanding, the duty cycle values ranges from the -PWM_PERIOD/2 to +PWM_PERIOD/2 when dead time is zero.

Here in my project, i am using switching frequency for PWM of 192KHz. With respect to this frequency, I can able to calculate the range with the SCLK of 112.5MHz in the below equation.

PWM_PERIOD = fSCLK/2 * desired frequency. // -292/2 to +292/2

But in our case, duty cycle value is calculated from the ADC input data which is 16bit to be write on duty cycle registers AH0,AH1,AL0,AL1. In which, I need to limit the range of duty cycle from 0% to 98%.

So here, the value of 16bit data is not within the limit of PWM_PERIOD.

Considering an example of having 16bit data in duty cycle register is,

*pREG_PWM1_DH0 = 0xFFFE;

*pREG_PWM1_DH1 = 0xFF15;

*pREG_PWM1_DL0 = 0xFFFE;

*pREG_PWM1_DL1 = 0xFF15;

How can we relate the range of duty cycle in percentage with my 16bit duty cycle value ?

can you please explain How can we convert the 16bit data into 100% which should be within the range of -PWM_PERIOD/2 to +PWM_PERIOD/2?

Thanks and Regards,

Velu