I've got a question about the SPORT in slave clock / framing mode (question is quite similar to the question here https://ez.analog.com/dsp/blackfin-processors/f/q-a/55817/bf51x-sport-start-in-clock-slave-mode), but the answer is not really clear to me. I need to fully understand how does the SPORT act when in slave mode because we need to handle that correctly in the software (many things are closely related to SPORT in out system, including some real-time management of radio hardware, which could lead to either hardware damage or clock jitter).
I've configured a SPORT channel to I2S mode, using DMA for transfers and external frame sync / clock signals (the codec is the master I2S device).
The TRFST and RFRST bits in SPORT configuration registers are set to 1 (Right stereo channel first) and the LFRS / RFRS bits are set to 1 (active low RFSx).
For debug purpose, I've set the transmitted buffer to 0xAA55AA55.
First question :
Here is what is obeserved on the SPORT bus :
As you can see, the first *valid* data sent is after a first I2S frame. I've checked that the sport was enabled at the time the I2S master device starts it clock (the sport is started about 375uS before the start of the BCLK signal on the above diagram)
Sometimes the codec (ADAU1361 from analog devices) do not start *correctly* (see the post here https://ez.analog.com/audio/f/q-a/166533/adau1361-i2s-startup-bclk-lrclk-synchronization) but the sport seems act correctly (with the exception of the first skipped frame). Can you explain why the *false* LRCLK signalling a right channel do not make the SPORT start ? Does it need the BLCK to tick during the LRCLK ?