UART example code BF533

Hi i am testing UART module of ADSP BF533 on board EZ Lite BF533. Could you give me an example code, which configure register to test UART module on the board. I have read the example in folder VisualDSP 5.1.2\Blackfin\Example, but all example is using adi library (which i do not use). I need an example code which configure directly value on UART register of BF533. 

Thank you!

  • 0
    •  Analog Employees 
    on Mar 25, 2020 1:18 PM 9 months ago


    Please find the example code for ADSP-BF533 UART loopback in the attachment. Please use this as a reference and modify as per your requirement.

    Hope this helps!

    Anand Selvaraj

  • Thank you for your support. I am confused with UART_DLL and UART_DHL registers. As i read in the Hardware reference document, i understand this two register is used to configure the baud rate of UART. But i do not know how to calculate the baud rate. For example, i need the baud rate is 9600 and my SCLK clock is 100 MHz, so what the value of UART_DLL and UART_DHL ?

    And with your example code, if i load your code to my board ADSP-BF533 EZ-Kit Lite, then i connect to my computer COM port, which baud rate shoul i set to my computer ? (i have modified it and remox the loop back part, just use TX to transmit a character) 

    One more thing, now i do not know the SCLK clock on board ADSP-BF533 EZ-Kit Lite by default. If i just turn the board on and do nothing with PLL, so what is the SCLK frequency ?

  • 0
    •  Analog Employees 
    on Mar 25, 2020 3:00 PM 9 months ago in reply to Thanh Nguyen

    The CLKIN crystal on the EZKIT is 27 MHz. Per the default settings of the PLL registers, this results in a CCLK of 270MHz and an SCLK of 54MHz. As to your UART questions, you will need to set your UART baud rate to match what you configure the baud rate to be on the target Blackfin processor (i.e., 9600, if that is how you configure the UART_DLH and UART_DLL registers). To that, if your SCLK is 100 MHz, then you use the equation documented in the HRM to compute:

    BAUD RATE = SCLK / (16 x Divisor)

    where Divisor is a 16-bit concatenation of the UART_DLH (upper byte) and UART_DLL (lower byte).

    9600 = 100,000,000 / (16 x Divisor)

    Divisor = 100,000,000 / (16 x 9600) = 100,000,000 / 153,600 = 651.04 = 0x028B

    Therefore UART_DLL = 0x8B and UART_DLH = 0x02


  • Hi i have tried the UART code  on ADSP BF533 EZ-Kit  Lite. I have connected the JP4 jumper on the board with my UART to USB module and connect the UART to USB module to USB port on my computer. On my computer, i used Tera term VT, but the character the i received on the computer is not true. Please see the result as below:

    My COM port setup on my computer is below:

    And my code have there three file uart.c, uart_test.h and uart_test.c. The source code is as blow:

    - In file uart_test.c:

    #include <sys/platform.h>
    #include "adi_initialize.h"
    #include "uart_test.h"

    char __argv_string[] = "";

    int main(int argc, char *argv[])
    char *s = "BBBBAAAAA";
    //*pUART_GCTL = 0x0001;
    while (1) {

    - In file uart_test.h:

    #ifndef __UART_TEST_H__
    #define __UART_TEST_H__

    #include <sys\exception.h>
    #include <cdefBF533.h>
    #include <ccblkfn.h>
    #include <sysreg.h>

    void initUART (void);
    void putc (char c);
    #endif /* __UART_TEST_H__ */

    - In file uart.c:

    #include "uart_test.h"

    void initUART (void)

    *pUART_LCR = 0x0080;// Enable access UART DLL DLH

    // set baud rate = 9600
    *pUART_DLH = 0x60;
    *pUART_DLL = 0x01;
    *pUART_LCR = WLS(8); // set data 8 bit word long

    *pUART_GCTL = UCEN; // enable clock UART

    // disable the divisor latch access
    *pUART_LCR = 0x0000;

    *pUART_IER = 0x0000; // disable clock, using polling for transmit



    void putc (char c)
    while (!(*pUART_LSR & THRE)) {};
    *pUART_THR = c;

    Please tell what i am wrong ?

  • 0
    •  Analog Employees 
    on Mar 26, 2020 12:15 PM 9 months ago in reply to Thanh Nguyen

    It looks like you transposed the settings of the DLH and DLL registers. With the above settings, the SCLK would be 3.775 GHz, which would obviously be WAY out of spec. If you switch it to DLH = 0x01 and DLL = 0x60, the SCLK would be ~54 MHz,