Hi, I am using kit BF533 EZ Lite Kit, and i have a question about signal clock of chip BF533.
Firstly, as my understanding the chip Blackfin BF533 do not have internal clock and it need to have an external clock provide to the BF533. Is this true ?
Second, the board BF533 EZ Lite Kit has two oscilator source is 32.768 kHz and 27 Mhz, so when i power it on, which clock source will be used for core clock and system clock ? As my understanding, it is 27 Mhz.
Third, when i power the board on, the default clock of module SPORT will be 27 Mhz on the RCLK an TCLK pin ? if i configure it for internall mode.
Moving to Blackfin Processors community
Hi,1) No, you should provide an external clkin to the BF533. Then passed based on the PLL configuration. The BF533 PLL will generate CCLK and SCLK. Please refer BF533 Hrm section "CHIP BUS HIERARCHY" at page no: 313. www.analog.com/.../ADSP-BF533_hwr_rev3.6.pdf2) Yes, your understanding is correct. The 32.768Khz is used for RTC. 3) Which sport you are using? By default the SPORT0 will connected with Audio codec. The Sport will configure for external clock and external frame sync.The SPORTs can operate at up to an SCLK/2 clock rate with an externally generated clock, or 1/2 the system clock rate for an internally generated serial port clock. The SPORT external clock must always be less than the SCLK frequency.Regards,Anand Selvaraj.
As in issue 3, i am using SPORT0 but i do not want to use external clock and frame sync frome code AD1836, i want to use clock and frame synch from BF533. Is it possible ?
4. And as reading in document, i know that SPORT can work in I2S mode or TDM mode. In TDM mode it can have more channels. So if i only have a codec with two channel, which mode should i choose: I2S or TDM ? what is the advantage and disadvantage of I2S (compare to TDM) ?
5. In document "ADSP-BF533 Blackfin Processor Hardware Reference" page 10-12, i see that BF533 have 7 SPO select flag, so it mean that BF533 only control 7 (maximum) codecs via SPI at a time ?
Hi Thanh,Sorry for the delay in response.1) Yes, you can generate sport clock internally using SPORTx_TCR1 register, SPORTx_TCLKDIV and SPORTx_TFSDIV registers. Refer BF533 Hrm topic "Clock and Frame Sync Frequencies" at page no: 536 in the below link.www.analog.com/.../ADSP-BF533_hwr_rev3.6.pdf2) Its is based on your requirement. In I2S mode data will received or transmitted as L channel and R channel. We can able to transmit/receive upto 32bit data in I2S mode. But in TDM mode data length will decreased, increase in no of channels.3) Please refer ez.analog.com/.../adsp-bf533-ez-kit-lite-sport-moduleRegards,Anand.S