BF527 SDRAM init


we have been using theBF527 with MT48H16M16LF   32MByte micron SDRAM for some years with the following initiations in the XML file:

EBIU_SDBCTL = 0x0013
EBIU_SDGCTL = 0x0091998d

We moved to MT48H32M16LF 64Mbyte micron SDRAM 

Moving to the new board, we initially used the original code and that worked fine (using only the lower 32M). 

When we work in the debugger setup we use an XML file with the above values.

Then we tried to use the whole 64M of the SDRAM,

we changed EBIU_SDBCTL = 0x0025 both in the XML file and in the run time code, and we saw that loading the code from debugger to SDRAM is incorrect. There are non-contiguous errors in the loaded code in the SDRAM so the software can’t run.

Does it means that the register setting in the XML file are wrong?

Although we used an example from Analog devices, maybe we missing something,

thank you for any suggestions.


  • 0
    •  Analog Employees 
    on Jan 17, 2020 9:45 AM 9 months ago

    Hi Shai,

    Sorry for the long delay.

    I would suggest you to refer the excel sheet which helps to calculate the correct SDR-/DDR1-/DDR2-SDRAM controller settings for the Blackfin processors External Bus Interface Unit (EBIU) as well as for the DDR2-SDRAM controller (DMC) for the latest generation Blackfin processors. In any case, refer to the SDRAM data sheet and the Hardware Reference Manual of your Blackfin processor derivative. In addition, there are few comments within the document that should be read as well.
    Excel sheet can be found here:

    Let me know if you are still facing any issues.

    Anand Selvaraj.