We are using an Ethernet PHY (KSZ8081MNX) with a BF536 and we have an issue with packets that are sometimes not sent on the network. We are able to sent packets, however sometimes some packets are not sent and the TX_MACE bit of the EMAC_TX_STKY Register is set. What does this bit actually mean ? We were not able to find any more information than "At least one internal MAC error was detected." from the hardware reference manual for the BF537. We are trying to identify if this is a hardware problem with our platform or if this is a software issue, but we would need more information about the TX_MACE bit to assess what is the issue.
The platform is using VDK and it's using lwip if it is any help. We are using VisualDSP IDE. The driver we are using for the PHY is based on the recommendations in the application note EE-315 Changing the PHY in the Ethernet Driver for Blackfin® Processors.
After investigating the issue a little more, I found out that there are DMA Underrun errors that are being raised by the EMAC (EMAC_TX_STAT bit TX_DMAU). What are the causes that could explain why the DMA is unable to feed the EMAC properly and cause a DMA underrun error ?
I found another post (https://ez.analog.com/dsp/blackfin-processors/f/q-a/55908/bf536-emac_tx_dmaund/96668#96668) which seems to have similar symptoms to what I am experiencing, however the root cause of the issue in that other post seems to be related to incorrect EBIU settings. I already validated my EBIU settings since I am using external SDRAM, but they seem fine.
I am also using cache memory for most of my application, however the memory used by the ethernet driver is placed in a non-cacheable memory region. Would it help to use cached memory instead of non-cacheable memory for the ethernet driver ? My understanding (from the hardware reference manual) is that it is not recommended to use cached memory for memory that will be also accessed by DMA.
I managed to fix the DMA underrun error by prioritizing DMA accesses over the Core for memory accesses. It was done by setting the CDPRIO bit in the EBIU_AMGCTL register.