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Best way to interface ADSP-SC584 with 2 LTC2344-18 ADCs

I am using ADSP-SC584 for a project. For the project I am interfacing 2 external ADCs and 2 external DACs with processor. I believe I can interface LTC2344-18 ADC to SC584 using SPORTs, or SPI or ACM. But since I am interfacing many external components, I don't want to use up too many pins.

What will be the best way to interface 2 LTC2344-18 ADCs to SC584 such that least number of serial communication pins gets consumed? Each ADC requires at least 4 serial outputs and 2 serial inputs ( 4 serial inputs, 2 serial output from SC584's perspective). For more information, here is the datasheet for LTC2344-18.

  • If your goal is to minimize the number of pins and you are willing to sacrifice throughput, you can share CNV, SCKI and SDO between the two ADCs and only have unique CSL lines for each ADC. This requires only a total of 5 lines for the two ADCs. The data from all four channels can be shifted through just SDO0 and by enabling each ADC through the CSL line all eight channels can be shifted through a single SDO pin.

  • Thanks. That is an interesting and useful suggestion. I have one more question regarding this. Is it possible for me to make SPORT work like SPI? I am particularly interested in making the CLK of SPORT work only when i want it to work, and the CLK should remain static the other times. Is it possible to do that in SPORT? Or does the CLK always keep running?

  • You will have to go to the appropriate forum for that question. Unfortunately, I am not familiar with the SPORT interface.

  • Hello,

    Yes it is possible. Gated clock mode support for internallly or externally generated clocks in DSP serial mode and stereo modes (left-justified and I2S mode)

    Please note that, some system components such as ADCs and DACs utilize a SPI-compatible protocol for the interface. To communicate with such devices, the SPORT must support a gated clock, where the data valid information is embedded in the clock (for example, the clock only toggles when data is valid). This gated clock feature is enabled using the SPORT_CTL_A.GCLKEN bit.

    Can you please refer the Gated Clock Mode section (PageNo: 2700 / 3973) in the HRM of ADSP-SC58x. For more information about SPORT, please have a look at PageNo: 2664 / 3973.
    www.analog.com/.../SC58x-2158x-hrm.pdf

    Regards,
    Lalitha.S