BF548M SPI1 and SPI2 with DMA for rx and tx

In my project  I want communication between BF548M processors using both SPI1(slave) and SPI2(Master) with DMA tx and rx both sides.

I have tested SPI1 and SPI2 individually both are working fine . But if I enable then together one of the SPI will not work.

I am attaching the code for SPI interface which i am using for testing .

Guys plz help me with the issue ?

// SPI_driver.c

#include <stdio.h>
#include <blackfin.h>
#include <sys/exception.h>



uint8_t receive_data[SPI_RX_BUFFER_SIZE];
extern uint8_t SPI_rx_data_port1[SPI_RX_BUFFER_SIZE] , SPI_rx_data_port2[SPI_RX_BUFFER_SIZE];
volatile int SPI_tx1_cnt , SPI_tx2_cnt ,SPI_rx1_cnt, SPI_rx2_cnt;
extern volatile  unsigned int SPI_tx_flag1,SPI_tx_flag2,SPI_rx_flag1 , SPI_rx_flag2 ;
/*******************************************************
* SPI0

SPI0SCK 	PE0
SPI0MOSI   PE2
SPI0MISO   PE1
SPI0SS     PE3

SPI0SEL1 	PE4     //For Master
SPI0SEL2 	PE5		// M
SPI0SEL3 	PE6		// M
********************************************************/

/*******************************************************
* SPI1
SPI1SCK 	PG8
SPI1MOSI   PG10
SPI1MISO   PG9
SPI1SS     PG11

SPI1SEL1 	PG5
SPI1SEL2 	PG6
SPI1SEL3 	PG7
********************************************************/
/*******************************************************
* SPI2
SPI2SCK 	PB12
SPI2MOSI   PB13
SPI2MISO   PB14
SPI2SS     PB8

SPI2SEL1 	PB9
SPI2SEL2 	PB10
SPI2SEL3 	PB11
********************************************************/
void SPI_pin_multiplex(uint8_t port , uint8_t mode)
{
	switch(port)
	{
	case 0:  // SPI0
		if(mode == 0)    // Slave
		{
			*pPORTE_FER |= 0x000f;
			*pPORTE_MUX &= 0xffff0000;

		}
		else if(mode == 1)  //Master
		{
			*pPORTE_FER |= 0x001f;
			*pPORTE_MUX &= 0xfffc0000;
		}
	break ;
	case 1:   // SPI1
		if(mode == 0)     // Slave
		{
			*pPORTG_FER |= 0x0f00;
			*pPORTG_MUX &= 0xff00ffff;
		}
		else if(mode == 1) // Master
		{
			*pPORTG_FER |= 0x0f20;
			*pPORTG_MUX &= 0xff00f3ff;
		}
	break ;
	case 2:  // SPI2
		if(mode == 0)  // Slave
		{
		*pPORTB_FER |= 0x7100;
		*pPORTB_MUX &= 0xc0fcffff;
		}
		else if(mode ==1)   // Master
		{
			*pPORTB_FER |= 0x7300;
			*pPORTB_MUX &= 0xc0f0ffff;
		}
	break ;

	default:
				printf("Invalid port number\n");
						break ;
	}
}

/****************************************************************************

****************************************************************************/
void SPI_Config(uint8_t port ,uint8_t mode , uint32_t spi_baud_rate , SPI_transfer_mode trans_m)
{
	switch(port)
	{
		case 1:        //SPI1

			*pSPI1_FLG = 0xFF02;    // Slave select enable 1
			*pSPI1_BAUD = spi_baud_rate;	 // SPI SCK frequency = SCLK / (2 X SPIx_BAUD)
			*pSPI1_CTL = 0;
			if(mode == 1)
			{

				*pSPI1_CTL = MSTR|EMISO|GM|SZ|trans_m;
			}
			else if(mode ==0)
			{
				*pSPI1_CTL = EMISO|PSSE|SZ|GM|trans_m;
			}
		break ;

    	case 2:			// SPI2
    		*pSPI2_FLG = 0xFF02;    // Slave select enable 1
			*pSPI2_BAUD = spi_baud_rate;		 // SPI SCK frequency = SCLK / (2 X SPIx_BAUD)
			*pSPI2_CTL = 0;
			if(mode == 1)
			{
				*pSPI2_CTL = MSTR|EMISO|GM|SZ|trans_m;

			}
			else if(mode == 0)
			{
				*pSPI2_CTL = EMISO|PSSE|SZ|GM|trans_m;
			}
		break ;
    	default:
    				printf("Invalid port number\n");
    						break ;
	}
}

/****************************************************************************

****************************************************************************/

EX_INTERRUPT_HANDLER(IsrSPI_withDMA_TX)
{
	if(*pDMA5_IRQ_STATUS & DMA_DONE)       //port1 tx
		{
			SPI_tx1_cnt++;
			while(*pDMA5_IRQ_STATUS & 0x0008);  		//poll on DMA_RUN bit
			*pDMA5_IRQ_STATUS |= 0x0001;

			while(*pSPI1_STAT & 0x0008);					//Check for Tx Buffer Empty
			while(!(*pSPI1_STAT & 0x0001));				//Check for SPIF
			SPI_tx_flag1 = 1;
			//*pSPI1_CTL &= ~SPE;							//Disable SPI

		}
	if(*pDMA23_IRQ_STATUS & DMA_DONE)     // port2 tx
		{
			SPI_tx2_cnt++;
			while(*pDMA23_IRQ_STATUS & 0x0008);  		//poll on DMA_RUN bit
			    *pDMA23_IRQ_STATUS |= 0x0001;

			    while(*pSPI2_STAT & 0x0008);					//Check for Tx Buffer Empty
			 	while(!(*pSPI2_STAT & 0x0001));				//Check for SPIF


			 //	*pSPI2_CTL &= ~SPE;							//Disable SPI
			 	SPI_tx_flag2 = 1;
		}
}
EX_INTERRUPT_HANDLER(IsrSPI_withDMA)
{
	if(*pDMA5_IRQ_STATUS & DMA_DONE)       //port1 rx
	{
		SPI_rx1_cnt++;
		*pDMA5_IRQ_STATUS |= DMA_DONE;
		while(!(*pSPI1_STAT & 0x0001));
		*pSPI1_CTL &= ~SPE;
		SPI_rx_flag1 = 1;
	}
	if(*pDMA23_IRQ_STATUS & DMA_DONE)     // port2 rx
	{
		SPI_rx2_cnt++;
		*pDMA23_IRQ_STATUS |= DMA_DONE;
		while(!(*pSPI2_STAT & 0x0001));
		//*pSPI2_CTL &= ~SPE;
		SPI_rx_flag2 = 1;


	}
}
void SPI_DMA_Config(uint8_t port , uint8_t *buff  , SPI_dir dir)
{
	if(port == 1)
	{		*pDMA5_CONFIG = 0x0;
			*pDMA5_START_ADDR= &buff[0];
			*pDMA5_X_COUNT = SPI_RX_BUFFER_SIZE;
			*pDMA5_X_MODIFY = SPIWdSize/8;
			*pDMA5_Y_COUNT = 0;
			*pDMA5_Y_MODIFY = 0;
			if(dir == SPI_RX)
				*pDMA5_CONFIG =  (0x0<<12)|(0x0<<8)|DI_EN|WNR;
			else if(dir == SPI_TX)
				*pDMA5_CONFIG =  (0x0<<12)|(0x0<<8)|DI_EN;
	}
	else if(port ==2)
	{
		*pDMA23_CONFIG = 0x0;
		*pDMA23_START_ADDR= &buff[0];
		*pDMA23_X_COUNT = SPI_RX_BUFFER_SIZE;
		*pDMA23_X_MODIFY = SPIWdSize/8;
		*pDMA23_Y_COUNT = 0;
		*pDMA23_Y_MODIFY = 0;
		if(dir == SPI_RX)
			{*pDMA23_CONFIG =  (0x0<<12)|(0x0<<8)|DI_EN|WNR;

			}
		else if(dir == SPI_TX)
			*pDMA23_CONFIG =  (0x0<<12)|(0x0<<8)|DI_EN;
	}
}
void SPI_Init_Interrupt(uint8_t SPI_num , SPI_DMAType mode)
{
	if(SPI_num == 1 && (mode == SPI_WithoutDMA))
	{
		SIC_EnableIntr(SIC_IRQ_SPI1_DMA5);
		register_handler(ik_ivg10,IsrSPI);
	}
	else if(SPI_num == 2 && (mode == SPI_WithoutDMA))
	{
		SIC_EnableIntr(SIC_IRQ_SPI2_DMA23);
		register_handler(ik_ivg10,IsrSPI);
	}
	else if(SPI_num == 1  && (mode == SPI_WithRXDMA))
	{
		
		SIC_EnableIntr(SIC_IRQ_SPI1_DMA5);
		register_handler(ik_ivg10,IsrSPI_withDMA);
		*pDMA5_CONFIG|=DMAEN ;   // enable DMA channel

	}
	else if(SPI_num == 2 && (mode == SPI_WithRXDMA))
	{

		register_handler(ik_ivg10,IsrSPI_withDMA);
		SIC_EnableIntr(SIC_IRQ_SPI2_DMA23);
		*pDMA23_CONFIG|=DMAEN ;  // enable DMA channel

	}
	else if(SPI_num == 2  && (mode == SPI_WithTXDMA))
				{
					SIC_EnableIntr(SIC_IRQ_SPI2_DMA23);
					register_handler(ik_ivg10,IsrSPI_withDMA_TX);
					*pDMA23_CONFIG|=DMAEN ;   // enable DMA channel

				}
	else if(SPI_num == 1  && (mode == SPI_WithTXDMA))
					{
						SIC_EnableIntr(SIC_IRQ_SPI1_DMA5);
						register_handler(ik_ivg10,IsrSPI_withDMA_TX);
						*pDMA5_CONFIG|=DMAEN ;   // enable DMA channel

					}
}