Controlling the data during the Sync pulse on the SPORT.


I am trying to create an interface to device requiring 3 channels of data synchronized with a common clock and a common sync signal. The data channels have a word length of 20 bits. The interface runs continuously with a bit period of 50ns, giving an overall cycle time of 2 microseconds.This means that the data in the transmit buffers is continuously re-transmitted until new data is loaded.

The setup code is shown below.

			*pSPORT0_TCR1 &= ~0x0001;		// Disable SPORT 0.
			*pSPORT1_TCR1 &= ~0x0001;		// Disable SPORT 1.

		    *pPORTGIO_DIR &= ~0x6000;		// SPORT1 TX clock & TX sync set to input mode.
		    *pPORTG_FER |= 0xe000;			// Enable SPORT1 TXP, TXC & TXS.
		    *pPORTGIO_INEN |= 0x6000;		// Input enable for SPORT1 clock & sync.
		    *pPORT_MUX |= 0x0800;			// Enable SPORT1 primary transmit.
			*pSPORT0_TCLKDIV = 32;			// Set clock speed - 2.02MHz @ SCLK = 133MHz.
			*pSPORT0_TFSDIV = 19;			// Gives sync pulse width equal to 1 data bit.
			*pSPORT0_TCR2 = 0x0112;			// 19 bit data length, secondary enabled.
			*pSPORT0_TCR1 = 0x2e02;			// Clock on rising edge, ...
											// ... data-independent, active-high TFS, ...
											// ... active-low sync, ...
											// ... external TX frame sync used, ...
											// ... external TX clock.
											// TCLKDIV ignored in external-clock mode.
											// TFSDIV ignored in external-sync mode.
			*pSPORT1_TCR2 = 0x0012;			// 19 bit data length, secondary disabled.
			*pSPORT1_TCR1 = 0x2c00;			// Clock on rising edge, ...
											// ... data-independent, active-high TFS, ...
											// ... active-low sync, ...
											// ... internal TX frame sync used, ...
											// ... internal TX clock.
			*pSPORT0_TCR1 |= 0x0001;		// Enable SPORT 0.
			*pSPORT1_TCR1 |= 0x0001;		// Enable SPORT 1.
			*pSPORT0_TX = 0x15001;			// SPORT0 Primary.
			*pSPORT0_TX = 0x18001;			// SPORT0 Secondary.
			*pSPORT1_TX = 0x2a501;			// SPORT1 Primary.

I get the first two data channels from SPORT0, using the primary and secondary data channels and generating the clock and sync internally. The third channel uses SPORT1, primary only and uses external clock and sync. The clock & sync signals for SPORT1 are taken from the corresponding signals generated by SPORT0 by connecting the appropriate pins.

This mostly works but I have noticed a couple of problems. To get a word length of 20 (including the sync period) I have to set a word-length of 19 (by inserting a value of 18). The data bit transmitted during the sync pulse is always 0, except when the MS bit in the data word is 1 and then the sync pulse data becomes 1. This seems very odd behaviour.

My problem is that I cannot control what is transmitted during the sync pulse, and while I can probably work round this I wondered whether there was anything else I could do within the setup to take control of the sync data bit.