Discrepancy in TWI section of Hardware Reference

Hi,

I've been going through the ADSP-BF51x Blackfin Processor Hardware Reference and I found what I think is a discrepancy.

1) On page 16-12, it instructs the user to write data to the TWI_XMT_DATA register before enabling the TWI.

2) In Figure 23-13, it instructs the user to first enable the TWI, and then wait for the XMTSERV interrupt before writing data to the TWI_XMT_DATA.

It seems to me that 1) is correct. Can anyone with experience with the TWI module shed some light on this?

Thanks,

Steve.

  • Steve,

    Without looking at the HRM, I think both of these might be valid, depending on context.  In the case where you are first enabling a TWI transfer, 1) is correct, but if you are in the middle of a multiple byte transfer then 2) is correct.  Here is a simple TWI routine that transfers two bytes of data that demonstrates this (note that this routine was written for 52x processor):

    void TWI_WRITE_2 (unsigned char addr, unsigned char MMR, unsigned char data)
    {

    int poll_timeout = 0;

    *pTWI_MASTER_ADDR = addr;//set slave address
    *pTWI_XMT_DATA8 = MMR;  //set MMR of the target chip
    *pTWI_MASTER_CTL = 0x0081; //specify num bytes (2), start xfer by writing 1 to en bit

    while (*pTWI_FIFO_STAT == XMTSTAT)//from twi.c

       asm("nop;"); 
       poll_timeout++;
      
       if (poll_timeout > MAX_POLL)
       { break;                }    //add error code here
    }

    *pTWI_INT_STAT = XMTSERV; // clear status

    *pTWI_XMT_DATA8 = data;

    //now, start polling to see if xfer complete
    while (!(*pTWI_INT_STAT & MCOMP))
      {  asm("nop;");  }
     
    *pTWI_INT_STAT = ( XMTSERV | MCOMP ); // service TWI for next transmission

    }

    Hope this helps,

    Ethan