Sampling frequency for amplitudes of each frequency of 150Hz to 3kHz

thank you very much for your reply.

I try to  generate the fft of any signal in the range of and

calculate the magnitude of each frequency

I use the SPI link between ADC and DSP Blackfin 533.

I want to know what value of sampling frequency should I use? (knowing that I

want to measure the amplitudes of each frequency of 150Hz to 3kHz)

Which registers do I put this value?

What is the values of registers SPI_BAUD, PLL_DIV?

how to calculate?

here the code for the initialization of the register SPI I use:

void Setup_SPI(void)

{

*pSPI_BAUD=0x0004;  // !!!

*pSPI_CTL=0x110a;  }

/ / in the main:

  • pPLL_DIV = 6;

PS: Blackfin DSP 533, ADC = AD7982.

I have read the datasheet, but I can not find the solution.

Please help me

2011/8/17 AndreasL <analog@sgaur.hosted.jivesoftware.com>

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  • Hi,

    as this is no longer related to the original VisualDSP++ Library question, and is about your application configuration, I have branched it to a new discussion and moved to the Blackfin category. Please continue the discussion here.

    Regards,
    Craig.

  • Hi,

    I try to  generate the fft of any signal in the range of 150Hz to 3KHz and calculate the magnitude of each frequency

    I use the SPI link between ADC and DSP Blackfin 533.

    I want to know what value of sampling frequency should I use? (knowing that I want to measure the amplitudes of each frequency of 150Hz to 3kHz)

    Which registers do I put this value?

    What is the values of registers SPI_BAUD, PLL_DIV?

    how to calculate it ?

    here the code for the initialization of the register SPI I use:

    void Setup_SPI(void)

    {

    *pSPI_BAUD=0x0004;  // !!!

    *pSPI_CTL=0x110a;

    *pSPI_FLG=4;

    }

    / / in the main:

    *pPLL_DIV = 6;

    PS: Blackfin DSP 533, ADC = AD7982.

    regards,

    Mathieu

    •  Analog Employees 
    on Aug 25, 2011 3:35 PM

    Hi Mathieu,

    The SPI Baud Rate register (SPI_BAUD) is used to set the bit transfer rate for a master device. When configured as a slave, the value written to this
    register is ignored. The serial clock frequency is determined by this formula:
    SCK Frequency = (Peripheral clock frequency SCLK)/(2 x SPI_BAUD)

    The SCLK frequency is programmed in the PLL_CTL and PLL_DIV registers.

    The relation between the CLKIN and VCO signal is determined by the values of DF bit and MSEL[5:0] in the PLL_CTL register(VCO=CLKIN*MSEL).Once the VCO is fixed using these two fields in PLL_CTL then the CCLK and SCLK can be obtained by programming values in CSEL and SSEL fields respectively in PLL_DIV register. By programming these registers suitably, you can get the desired SCLK frequency.Also note that the PLL programming sequence must be executed for these changes to take effect. "Dynamic Power Management Controller" chapter in the BF533 HRM would help you in understanding more on this.

    Thanks,

    Vinod

  • Thank you very much Vinod for your help, can you give me a code example for programming this please.

    Mathieu

  • What's is : SCK  and Peripheral clock frequency SCLK  ??

    how can i change the sampling frequency of ADC ??