Bug in BF561 booting example

I just want to alert everyone that there is a bug in the set_PLL routine in the Booting example for the BF561.

The temporary storage for SICA_IWR0 and SICB_IWR0 is of type short, while the register is actually 32 bit. This causes the two most significant bytes to be set to 0x0000 if bit 15 if 0 and 0xFFFF if bit 15 is 1. This has caused me much headache, since this function was used in a project I inherited. To be fair though, it did also cause me to find a significant bug in my own code

Here's the offending code:

short previous_SICA_IWR = *pSICA_IWR0;

*pSICA_IWR0 = (previous_SICA_IWR | 0x1); // enable PLL Wakeup Interrupt

*pPLL_CTL = new_PLL;
ssync();

idle();                                     // put in idle

*pSICA_IWR0 = previous_SICA_IWR;            // continue here after idle, restore previous IWR content

    •  Analog Employees 
    on Nov 17, 2011 2:10 AM

    Hi Rai,

    Thanks for letting us this know. Looks like all the 'set_PLL.c' files used in some more projects have same bug. I will re-route your suggestions to our internal team.

    Thanks,

    PG

    •  Analog Employees 
    on Nov 29, 2011 11:36 PM

    Hi Rai,

    The suggestions forwarded to our internal team are:

    - define the 'previous_SICx_IWR' local variables as unsigned int datatype and

    - change the PLL wake-up interrupt enable instructions in the PLL programming sequence. It is enabled as follow:

    *pSICA_IWR0 = (previous_SICA_IWR | 0x1);      // enable PLL Wakeup Interrupt
    *pSICB_IWR0 = (previous_SICB_IWR | 0x1);      // enable PLL Wakeup Interrupt

    So, if SICx_IWR registers are enabled for some other wake-up interrupts (before calling Set_PLL function), above instructions keeps these wake-up interrupts in enabled state (alongwith PLL Lock wake-up interrupt) while programming PLL. So, there can be a possibility that processor may come out of 'idle()' loop of PLL locking sequence because of other wake-up interrupts (which are kept in enabled state) and not bacause of PLL lock wake-up interrupt, resulting in incorrect PLL sequence.

    So, change the above lines to

    *pSICA_IWR0 = 0x1;      // enable PLL Wakeup Interrupt
    *pSICB_IWR0 = 0x1;      // enable PLL Wakeup Interrup

    This has been logged in our bug tracking database, and will be reviewed for a future release of the tools.

    Thanks,

    PG