I just want to alert everyone that there is a bug in the set_PLL routine in the Booting example for the BF561.
The temporary storage for SICA_IWR0 and SICB_IWR0 is of type short, while the register is actually 32 bit. This causes the two most significant bytes to be set to 0x0000 if bit 15 if 0 and 0xFFFF if bit 15 is 1. This has caused me much headache, since this function was used in a project I inherited. To be fair though, it did also cause me to find a significant bug in my own code
Here's the offending code:
short previous_SICA_IWR = *pSICA_IWR0;
*pSICA_IWR0 = (previous_SICA_IWR | 0x1); // enable PLL Wakeup Interrupt
*pPLL_CTL = new_PLL;
idle(); // put in idle
*pSICA_IWR0 = previous_SICA_IWR; // continue here after idle, restore previous IWR content