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ADSP-BF70x
  • Processors and DSP
  • Blackfin Processors
  • ADSP-BF70x
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ADSP-BF70x
Documents FAQ: How can I initialize DDR memory device connected to BF70x processor ?
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  • ADSP BF706 Ezkit Mini SPI1 cannot be done in master mode.
  • +ADSP-BF707: FAQ
  • -ADSP-BF70X: FAQ
    • Different Wake-up Sources on BF70x
    • FAQ: ADSP-BF70x application cannot boot using Secure Boot
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    • FAQ: Enhancements in Supervisor Mode in Blackfin+ core
    • FAQ: HADC maximum bandwidth
    • FAQ: Highlights of MSI on BF70x
    • FAQ: How can I initialize DDR memory device connected to BF70x processor ?
    • FAQ: How do I access the full memory space of the SPI slave?
    • FAQ: How L2CTL in BF70x is different than BF60x ?
    • FAQ: How the System Cross Bar (SCB) in BF70x different than in BF60x ?
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  • FAQ: BF707 SPI Slave to Master loopback communication

FAQ: How can I initialize DDR memory device connected to BF70x processor ?

BF70x processor's Dynamic Memory Controller (DMC) supports interface to DDR2 and LPDDR memory devices.The DMC must be configured to perform an initialization sequence as per the memory device specifications and application requirements. There are two types of DMC Initializations which may be required by an application using DMC:

1. Initialization for loading static code/data: This is required to be able to load any static code and (or) data to the DDR memory. While loading the code/data in the IDDE, this is done with the help of an xml file. To enable this, the option "Target->Settings->Target Options->Use xml reset values" should be checked. By default the IDDE uses the CGU and DMC reset values as defined in the "ADSP-BF707-resets.xml" file available in the folder "<Installation directory>\CrossCore Embedded Studio 1.1.0\System\ArchDef".  The default clock settings used are: PLLCLK=800 MHz, CCLK=400 MHz, SYSCLK=200 MHz, SCLK0=100 MHz, SCLK1=200 MHz and the DMC settings are for the DDR2 memory device MT47H128M16RT-25E.  For any custom CGU/DMC settings, it is recommended to use the custom board support file which can be selected by enabling customizations in the debug configuration settings as shown in the below screenshot.

For example, the attached file "lpddr_custom_board_support.xml" overrides the default DMC settings in the ADSP-BF707-resets.xml and configures the controller for the LPDDR device MT46H128M16LFB7-5.

Similarly, when the code is booted standalone without using an emulator, the boot code does the job of configuring the DMC as per the DDR2/LPDDR memory device connected to the processor for initializing any static code/data. The init code which comes with CCES by default configures the DMC for the DDR2 memory device MT47H128M16RT-25E available on the BF707 EZ-Kit. This can be modified easily by changing the DDR2 parameters in the file "init_memory.h". For LPDDR init code, the attached files "init_memory.h" and "init_memory.c" should be used instead of the default files. Also, the following line in the init_code.c should be modified to call the function "DMC_Init_LPDDR" instead of  "DMC_Init_DDR2".

#if defined(__CONFIG_MEMORY__)

        DMC_Init_DDR2();

#endif

2. Initialization for dynamic accesses: Most of the times, the static initialization (performed with the help of xml file or  init code) can be used even for accessing the DDR2/LPDDR memory for accessing external code/data while executing application code. But in some cases where a different CGU/DMC settings are required in the application code, the DDR2 and LPDDR Initialization code supplied with the init code can be used as reference to write a custom DDR2/LPDDR Initialization code sequence.

Attachments:
8461.init_memory.c.zip
4705.init_code.c.zip
2043.init_memory.h.zip
4527.lpddr_custom_board_support.xml.zip
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