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ADSP-BF70x
  • Processors and DSP
  • Blackfin Processors
  • ADSP-BF70x
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ADSP-BF70x
Documents FAQ: How to re-enable the Core clock on BF70x after gating it
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  • ADSP BF706 Ezkit Mini SPI1 cannot be done in master mode.
  • +ADSP-BF707: FAQ
  • -ADSP-BF70X: FAQ
    • Different Wake-up Sources on BF70x
    • FAQ: ADSP-BF70x application cannot boot using Secure Boot
    • FAQ: CPLB enhancements in Blackfin+ Core
    • FAQ: Different Wake-up Sources on BF70x
    • FAQ: Digital watch code for RTC
    • FAQ: Enhancements in Hardware Loop in Blackfin+ core
    • FAQ: Enhancements in Supervisor Mode in Blackfin+ core
    • FAQ: HADC maximum bandwidth
    • FAQ: Highlights of MSI on BF70x
    • FAQ: How can I initialize DDR memory device connected to BF70x processor ?
    • FAQ: How do I access the full memory space of the SPI slave?
    • FAQ: How L2CTL in BF70x is different than BF60x ?
    • FAQ: How the System Cross Bar (SCB) in BF70x different than in BF60x ?
    • FAQ: How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation
    • FAQ: How to re-enable the Core clock on BF70x after gating it
    • FAQ: How to send data using SPI READY signal
    • FAQ: How to take the core out of reset on BF70x
    • FAQ: How to use the Signtool Utility to encrypt and sign the unsigned bootstream (loader file generated for an application, example:bootstream.ldr)
    • FAQ: Is INIT Code supported in Secure Boot in ADSP-BF707
    • FAQ: Monitoring Cache Performance on the ADSP-BF70x
    • FAQ: Performance Enhancements in Blackfin+ core
    • FAQ: UART slave boot BF70x with Higher BAUD rate
    • FAQ: Sample code for HADC on BF70x?
    • FAQ: What are the salient features of SPI Host Port on BF70x?
    • FAQ: What is the effect of bus disabling (RDEN bit) on RTC functionality?
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    • FAQ: What is the purpose of the ownership bit when programming the PKTE module for encryption/hashing?
    • FAQ: What modes of Encryption and Hashing are supported and how do they make an application secure
    • Getting Started with ADSP-BF70x Processors
    • How to re-enable the Core clock on BF70x after gating it
    • Known Errata Against ADSP-BF70x Blackfin+ Datasheet
    • the secret BF70x documentation
    • Where can I find power consumption data for BF70x processors?
    • FAQ: What are the major differences between DMC module of BF60x and BF70x ?
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    • FAQ: Can I pass the output generated from PKA directly to the PKTE module for encryption/decryption
    • FAQ: Configuring Timer in continuous/single pulse mode
  • Example for UART transmit and receive operation using Core Mode for BF707
  • FAQ: BF707 SPI Slave to Master loopback communication
  • FAQ: Hardware Reset using Watchdog in BF706

FAQ: How to re-enable the Core clock on BF70x after gating it

Since BF70x is a single core processor, gating the core clock can make the core unrecoverable since the core can not re-enable its own clock once it has disabled it. However using the system infrastructure properly can allow for the Core clock to be restored. The attached code examples demonstrates this by using the TRU along with DMA to re-enable the core clock and enable the core to execute.

Code does following:

  • Map the GPIO (pushbutton on EZKIT) trigger to MDMA
  • Configure the MDMA to write to CGU_CCBF_DIS to enable the clock back
  • Disable the Core clock
  • Put the core in IDLE
  • Wait for Push button press
  • Pushing the push button trigger the DMA to enable the Core clock

This FAQ was generated from the following discussion: How to re-enable the Core clock on BF70x after gating it

Attachments:
2548.CGU_CoreClockGate_TRU.rar.zip
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