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1. Instruction Cache Way Locking:
The instruction cache way locking feature is no longer supported in new Blackfin+ core.
2. Direct access to cache and Instruction memory space:
Blackin+ processor support new mode called Extended Data Access mode. In this mode , direct access of the L1 Data cache memory, L1 instruction cache memory and L1 instruction memory is allowed. This mode can be enabled by setting ENX bit in L1_DM_DCTL register. Cache Tag memory, Dirty State memory can be directly read from the cache memory space and cache invalidation can be done by directly writing into cache memory. DTEST_COMMAND and ITEST_COMMAND registers which provided a back door access to the cache memory are no longer supported in Blackfin+ core and Run-timer libraries also make use of Extended Data Access mode.