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Documents How to take the core out of reset on BF70x
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  • +ADSP BF706 FAQ:
  • +ADSP-BF707: FAQ
  • -ADSP-BF70X: FAQ
    • Different Wake-up Sources on BF70x
    • ADSP-BF70x application cannot boot using Secure Boot
    • CPLB enhancements in Blackfin+ Core
    • FAQ: Different Wake-up Sources on BF70x
    • Digital watch code for RTC
    • Enhancements in Hardware Loop in Blackfin+ core
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    • HADC maximum bandwidth
    • Highlights of MSI on BF70x
    • How can I initialize DDR memory device connected to BF70x processor ?
    • How do I access the full memory space of the SPI slave?
    • How L2CTL in BF70x is different than BF60x ?
    • How the System Cross Bar (SCB) in BF70x different than in BF60x ?
    • How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation
    • FAQ: How to re-enable the Core clock on BF70x after gating it
    • How to send data using SPI READY signal
    • How to take the core out of reset on BF70x
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    • Getting Started with ADSP-BF70x Processors
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    • ADSP-BF70X BLACKFIN PROCESSOR SUPPORT COMMUNITY
    • DMA error interrupt
    • How to verify that the boot bytes are accurate in all boot modes for the ADSP-BF60x and ADSP-BF70x?

How to take the core out of reset on BF70x

Q:

How do you take the core out of reset on the ADSP-BF70x?

--------------

A:

Since BF70x is a single core processor, the core resetting itself is not recommended because once the core puts itself in reset there is no way the core can take itself out of reset. However with the use of DMA and TRU core can be taken out of reset state by programming the TRU in such a way that on user request MDMA is triggered and writes to the Core reset register to take the core out of reset.

The code attached here demonstrates this. The code does following:

  • Core programs TRU such that the Core 0 System Interface Disable Acknowledge (C0_SI_DIS_ACK) is assigned to Core-Reset (RCU0_C0RST) slave trigger.
  • PINT0 trigger(for PA_02, push-button on EZKIT) is assigned to master trigger for MDMA0
  • MDMA descriptors are set up to de-assert the RCU’s reset request.
  • Core programs disable request in RCU (RCU0_SIDIS.SI0) and then goes to IDLE.
  • SVECT0 is loaded with the address of LED blink code in L2 memory
  • As a result of this disable request, the Core completes any outstanding transactions on its interfaces and asserts the Core disable acknowledge. This is connected to the C0_SI_DIS_ACK master trigger of the TRU, and results in Core-Reset Slave trigger to be asserted. This results in the Core getting reset via the RCU. Core is in REST now.
  • When user proesses the Push button 2, MDMA0 is triggered and core is taken out of reset.
  • Having been reset, the Core begins executing from the address in SVECT0.
Attachments:
1565.RCU_HardCoreReset.zip
Tags: reset bf70x
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