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  • +ADSP BF706 FAQ:
  • +ADSP-BF707: FAQ
  • -ADSP-BF70X: FAQ
    • Different Wake-up Sources on BF70x
    • ADSP-BF70x application cannot boot using Secure Boot
    • CPLB enhancements in Blackfin+ Core
    • FAQ: Different Wake-up Sources on BF70x
    • Digital watch code for RTC
    • Enhancements in Hardware Loop in Blackfin+ core
    • Enhancements in Supervisor Mode in Blackfin+ core
    • HADC maximum bandwidth
    • Highlights of MSI on BF70x
    • How can I initialize DDR memory device connected to BF70x processor ?
    • How do I access the full memory space of the SPI slave?
    • How L2CTL in BF70x is different than BF60x ?
    • How the System Cross Bar (SCB) in BF70x different than in BF60x ?
    • How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation
    • FAQ: How to re-enable the Core clock on BF70x after gating it
    • How to send data using SPI READY signal
    • How to take the core out of reset on BF70x
    • How to use the Signtool Utility to encrypt and sign the unsigned bootstream (loader file generated for an application, example:bootstream.ldr)
    • Is INIT Code supported in Secure Boot in ADSP-BF707
    • Monitoring Cache Performance on the ADSP-BF70x
    • Performance Enhancements in Blackfin+ core
    • UART slave boot BF70x with Higher BAUD rate
    • Sample code for HADC on BF70x?
    • What are the salient features of SPI Host Port on BF70x?
    • What is the effect of bus disabling (RDEN bit) on RTC functionality?
    • What is the Encrypt-Hash and Hash-Decrypt mode in PKTE module
    • What is the purpose of the ownership bit when programming the PKTE module for encryption/hashing?
    • What modes of Encryption and Hashing are supported and how do they make an application secure
    • Getting Started with ADSP-BF70x Processors
    • How to re-enable the Core clock on BF70x after gating it
    • Known Errata Against ADSP-BF70x Blackfin+ Datasheet
    • the secret BF70x documentation
    • Where can I find power consumption data for BF70x processors?
    • What are the major differences between DMC module of BF60x and BF70x ?
    • Cache Enhancements in Blackfin+ core
    • Can I pass the output generated from PKA directly to the PKTE module for encryption/decryption
    • Configuring Timer in continuous/single pulse mode
    • ADSP-BF70X BLACKFIN PROCESSOR SUPPORT COMMUNITY
    • DMA error interrupt
    • How to verify that the boot bytes are accurate in all boot modes for the ADSP-BF60x and ADSP-BF70x?

DMA error interrupt

Processor: ADSP-BF70x

All the DMA error interrupts are combined into a single shared interrupt. Combined error signals require reading the DMA_STAT register of each DMA channel associated with a combined error interrupt to determine the DMA channel responsible for the generation of the interrupt.

The interrupt ID for DMA error is 26(SYS_DMAC_ERR). It is available in the HRM under "Table 8-2: ADSP-BF70x Interrupt List"(Page No: 266/2223).

For more information, please refer the ADSP-BF70x Hardware reference manual. The link is given below.
https://www.analog.com/media/en/dsp-documentation/processor-manuals/BF70x_BlackfinProcessorHardwareReference.pdf

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