Question 1

How to verify that the boot bytes are accurate in all boot modes for the ADSP-BF60x and ADSP-BF70x?

Accepted Answer

ADSP-BF60x/BF70x features CRC32 protection is implemented in hardware. The boot kernel provides mechanisms to allow each block to be verified using a 32-bit CRC. 
 When building a LDR file for CRC32 protection, use the -CRC32 <PolynomialCoefficient> switch. -CRC32 (PolynomialCoefficient) 
 The -CRC32 switch directs the loader to generate CRC32 checksums. It uses the polynomial coefficient if specified, otherwise uses the default coefficient (0xD8018001).

Question 2

How do I access the full memory space of the SPI slave?

Accepted Answer

Q: 
 How do I access the full memory space of the SPI slave? 
 -------------- 
 A: 
 In order to provide unconstrained access to the full memory space of the SPI slave, address translation is supported. The SPI host provides the 24-bit address to the SPIHP. The SPIHP base address register holds the 8-bit address offset to be pre-pended to the address supplied by the host. The base address offset (BAO) value of the selected SPIHP_BAR[n] register is used as bits 31–24 for the local address. 
 For instance, If the master wants to access L1 SRAM(0x11800000), the SPIHP_BAR0 register is programmed with a value 0x11(upper 8-bits of target memory location) and the master will send the 24-bit address 0x800000 along with the opcode.

Question 3

How the System Cross Bar (SCB) in BF70x different than in BF60x ?

Accepted Answer

The SCB fabric in BF70x has the following major differences as compared to that in BF60x: 
 - The SCB arbitration in BF60x is programmed in terms of number of read/write channel slots while in BF70x, the arbitration is programmed in terms of the read/write Quality of Service (OQS) value. Each master is associated with its own read/write QOS value. This value is used by the SCBs at various levels to arbitrate among various masters. For more details, please refer BF70x HRM. 
 - The SCB fabric in BF70x has "Interface Block Sync Mode" registers to program the clock domain crossing (async/1:1/1:n/n:1) across various clock domains (e.g. SYSCLK:DCLK, SCLK1:SYSCLK etc). This helps in improving the throughput across the fabric. This option is not available in BF60x.

Question 4

How L2CTL in BF70x is different than BF60x ?

Accepted Answer

The L2CTL module of the BF70x has the following differences as compared to BF60x: 
 - The L2 SRAM size in BF70x is 1 Mega Bytes with eight banks of size 128 KB each. While in BF60x the L2 SRAM size is 256 KB with each bank of size 32 KB. 
 - The L2 ROM size in BF70x is 512KB. While in BF60x the L2 ROM size is 32KB. 
 - The L2CTL in BF70x supports ECC error detection for ROM as well. While it is not supported in BF60x. 
 - The L2CTL in BF70x supports automatic H/W initialization of all the L2 SRAM banks. For BF60x, it has to be done in the software. 
 -The memory scrub/refresh procedure in BF70x is different than in BF60x. In BF60x, the refresh has to be done one by one by writing to the L2CTL_RFA register. In BF70x, a block of data can be refreshed at a time by writing the start address and count registers. 
 - Unlike in BF60x, the L2CTL in BF70x has one additional interrupt called as scrub/init done interrupt to indicate the completion of scrub/init procedure. 
 - For power saving, the L2CTL in BF70x have two low power mode options called as deep sleep and shut down mode.

Question 5

Configuring Timer in continuous/single pulse mode

Accepted Answer

In single-pulse PWMOUT mode, the timer generates a single pulse on the TIMER_TMR[n] pin. This mode is frequently used to implement a precise delay, often with generating an output trigger. In continuous PWMOUT mode, the timer generates a repetitive pulse with a well-defined period, duty cycle, and pulse position. The BF707 timer is configured in continuous/single pulse mode. In continuous pulse mode timer will interrupt every 1ms. We added an LED toggling in the Timer0 ISR and confirmed that it toggles always in a period of 1 Sec, which is configured in TMR0 period register in the code. 
 Timer0_interrupt.zip

Question 6

What is the effect of bus disabling (RDEN bit) on RTC functionality?

Accepted Answer

Setting this bit disables the output buses between RTC I/O voltage domain and RTC core voltage domain. It prevent floating node consumption when the RTC is not used. When this bit is set, the oscillator and counters will continue to function but neither of RTC_CLOCK or RTC_ALARM or RTC_SWTCH registers will be updated, also interrupts are not generated.

Question 7

How to send data using SPI READY signal

Accepted Answer

The BF707 will used as a host. It will send data, when SPI_RDY pin is low. The BF609 will used as a SPI slave. The SPI_RDY pin must have 10K pull up resistor. The connection are given as below. BF707 SPI Host BF609 SPI slave SPI2_CLK (P1B 107) SPI1_CLK(P1B_82) SPI2_MOSI(P1B 108) SPI1_MOSI(P1B_84) SPI2_SSEl1(P1B 110) SPI1_SSEL1(P1B_39) SPI2_RDY(P1B 48) SPI1_RDY(P1B_50) The SPI MUX and FER register configured using addin plug in system.svc. 
 
 SPI_MASTER_BF707.zip 
 ADSP-BF609_SPI_Receive.zip

Question 8

Highlights of MSI on BF70x

Accepted Answer

Following are the highlights of Mobile Storage Interface Module on BF70x processors: 
 
 MSI has an integrated DMA controller to transfer data between the FIFO and system memory 
 Core accesses to MSI FIFO are not supported 
 Supports Secure Digital memory protocol (version 3.0), • Supports Secure Digital I/O protocol (version 3.0), Multimedia Card protocol (MMC - version 4.41, eMMC 4.5) 
 Support for automatically generating the STOP command after data transfer(MULTI-BLOCK or STREAM) is finished 
 Flexible FIFO and card threshold controls 
 MMC boot mode support 
 
 This FAQ was generated from the following discussion: Highlights of MSI on BF70x

Question 9

What is the Encrypt-Hash and Hash-Decrypt mode in PKTE module

Accepted Answer

Q: 
 What is the Encrypt-Hash and Hash-Decrypt mode in PKTE module? 
 -------------- 
 A: 
 PKTE module allows the encryption and hashing to be done in parallel. For this two modes are supported. Encrypt-Hash and Hash-Decrypt. 
 Encrypt-Hash operation mean that the ciphertext obtained from the encryption for a given source input (plaintext) will be used as an input for hashing and then it will produce hash message digest output. So final result will hold the following: 
 
 The ciphertext(encrypted output) for a given input 
 The hash message digest output for a ciphertext generated in step a. 
 
 Hash-Decrypt will do the reverse operation of Encrypt-Hash. It will take the ciphertext as input source and will generate the hash message digest output and plaintext(decrypted output) from the ciphertext.

Question 10

UART slave boot BF70x with Higher BAUD rate

Accepted Answer

Attached is the example codes to test the UART slave boot with Higher BAUD rate on ADSP-BF70x. As a first stage loader, the &ldquo;BF70x_Bootrom&rdquo; project is used. When calling &ldquo;adi_rom_boot()&rdquo;, the autobaud detection is disabled and provided the UART clock (0xA) as per the SCLK of 100MHz, this is configured via UART Slave Boot command. After reset (UART slave boot mode is set in the BF707 slave), need to send the BF70x_Bootrom LDR via LDR viewer utility (this happens in the lesser baud rate). Now the slave processor executes this to change the CGU and then invoke adi_rom_boot() API, now the slave DSP is waiting for the next LDR to load. Then, use the another HOST processor (BF707) as UART host which send the &ldquo;application&rdquo; ldr at the baud rate of 622000. 
 BF70x_Bootrom.zip 
 BF707_Uart_Slave_Boot_Host.zip

Question 11

What are the major differences between DMC module of BF60x and BF70x ?

Accepted Answer

Following are some differences between the DMC of BF60x and BF70x: 
 - The DMC controller in BF70x is similar to a great extent to the controller in BF60x with some enhancements. For example, the DMC controller in BF70x supports an internal read data buffer which acts as a small cache and thus can improve the overall efficiency. 
 - The DMC PHY in BF70x is completely different than the PHY in BF60x. The drive impedance and the on die termination programming is done differently in BF70x. It supports auto-calibration of the drive impedance and the ODT values and thus has much more granular control over these values as compared to the DMC PHY in BF70x. 
 - The programming model of the DMC in BF70x is similar to that in BF60x except that the user need to make sure that the drive impedance and ODT calibration is done well before the initializing the DMC module. 
 For more information, please refer BF70x Hardware Reference Manual.

Question 12

How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation

Accepted Answer

In Dual Buffer descriptor mode, each descriptor can transfer the data from two different buffers with buffer size up to 4096 bytes. In this mode IDMAC can either use only one descriptor to transfer the data from two buffer or it can have multiple descriptors which can be chained to run one after the other. Unlike the chained descriptor mode where the descriptor has the address of next descriptor, dual buffer mode links the descriptors using a fixed offset between the end address of current descriptor and start address of next descriptor. This fixed offset is same for all the descriptors in the chain and is programmed in DSL(Descriptor Skip Length) field of MSI_BUSMOD register. 
 Forming a ring chain of descriptors in dual buffer mode is also possible. This is helpful if the same set of descriptors need to be used again and again in a ring form. In order to configure the IDMAC descriptors in Dual buffer ring mode, use following steps: 
 
 Set up the 'N' IDMAC descriptors in the Host memory with different descriptor elements like Buffers sizes, Buffer addresses programmed appropriately. 
 For the first descriptor, FS(First Descriptor) bit in the first descriptor element should be set to inform the IDMAC that this is the first descriptor. In addition OWN bit should also be set. 
 For Descriptor 2 to Descriptor N-1, OWN bit in the first descriptor element should also be set. 
 For descriptor N(last descriptor in the ring), EOR bit should be set. This informs the IDMAC to load the first descriptor address after finishing the Nth descriptor thus forming a ring. 
 Enable the IDMAC interrupt. Normally IDMAC interrupt occurs when each descriptor finishes. However the individual descriptor interrupt generation can be disabled by setting the DIC(Disable Interrupt on Completion) bit in the descriptor 
 When the last descriptor interrupt occurs, update all the descriptors in the chain. Do following:
 
 Update the Buffer addresses for each descriptor 
 Set the OWN bit for each descriptor(as the IDMAC clears this bit once it executes the descriptor) 
 Write to PLDMND register with any non-zero value to cause the re-fetch of the descriptor. 
 
 Do this as long as the software needs the descriptor ring to continue. 
 Before the last iteration of the Ring, do the following additional steps(in addition to above mentioned steps) in the last descriptor interrupt :
 
 Clear the EOR bit of last descriptor 
 Set the LD (Last Descriptor ) bit of the last descriptor. 
 
 With EOR cleared and LD set in the last descriptor, the descriptor chain breaks and the IDMAC closes the descriptor operation.

Question 13

What modes of Encryption and Hashing are supported and how do they make an application secure

Accepted Answer

Q: 
 What modes of Encryption and Hashing are supported and how do they make an application secure? 
 -------------- 
 A: 
 The ADSP-BF707 comprises of the three crypto modules : 
 Security Packet Engine, Public Key Accelerator(PKA) and True Random Number Generator(TRNG). 
 The Security packet engine supports AES-128/192/256, DES, TDES modes of encryption and SHA-1, SHA-224 and SHA-256 modes for hashing algorithms. This module provides symmetrical mode of encryption/decryption. 
 In order to make it more secured, it can be used together with PKA which can be used to implement algorithms like RSA, ElGamal and Digital Signatures like ECDSA etc. 
 Also TRNG can be used to provide random numbers which can be used to provide random initialization vectors, keys etc. 
 All three modules if used together can be used to implement a very secured system in ADSP-BF707.

Question 14

Monitoring Cache Performance on the ADSP-BF70x

Accepted Answer

Question 
 How do I monitor cache performance on the ADSP-BF70x? 
 =========================================== 
 Answer 
 The performance monitor can count events like cache misses non-intrusively. The following functions can be added to your program and used to start and stop monitoring events of interest. 
 #include <sys/platform.h>

typedef enum {
 /* BF70x cache related events.
 Refer to Programmers Reference for others.
 */
 pf_icache_hit = 0x81,
 pf_icache_miss = 0x82,
 pf_dcache_fill_completed = 0x98,
 pf_dcache_line_replaced = 0x99,
 pf_dcache_hit = 0x9a,
 pf_dcache_miss = 0x9b
} PFMonEvent;

void start_pfmon(PFMonEvent mon0, PFMonEvent mon1) {
 uint32_t ctl = 0;
 if (mon0)
 ctl |= BITM_PFCTL_PWR|
 (3<<BITP_PFCTL_ENA0)|
 ((mon0<<BITP_PFCTL_MON0)&BITM_PFCTL_MON0);
 if (mon1)
 ctl |= BITM_PFCTL_PWR|
 (3<<BITP_PFCTL_ENA1)|
 ((mon1<<BITP_PFCTL_MON1)&BITM_PFCTL_MON1);
 *pPFCTL = 0;
 *pPFCNTR0 = 0;
 *pPFCNTR1 = 0;
 *pPFCTL = ctl;
}

void stop_pfmon(unsigned *count0, unsigned *count1) {
 ssync(); /* flush system activity before stopping counting */
 *pPFCTL = 0;
 if (count0)
 *count0 = *pPFCNTR0;
 if (count1)
 *count1 = *pPFCNTR1;
}

These functions can be used to monitor cache activity in your program as follows. 
 unsigned dcache_hits, dcache_misses;
start_pfmon(pf_dcache_hit, pf_dcache_miss);
...
/* code you want to monitor */
...
stop_pfmon(&dcache_hits, &dcache_misses);
printf("dcache hits = %u, dcache misses = %u", dcache_hits, dcache_misses);

Question 15

Enhancements in Supervisor Mode in Blackfin+ core

Accepted Answer

1.Supervisor Access bit 
 The new Blackfin+ core support entering supervisor mode through setting SACC(supervisor Access bit ) bit of SYSCFG register. When the SACC bit is set , processor allows supervisor access even when not servicing interrupt or exception. When SACC bit is cleared , supervisor access is permitted only when servicing interrupt or exception. Hence processor will be in supervisor mode ,When servicing an interrupt, a nonmaskable interrupt (NMI), an exception, or when SACC bit is set .This new feature will remove the restriction on supervisor access only when servicing interrupt or exception. 
 The User Stack Pointer (USP) register will be used when not servicing an interrupt, a nonmaskable interrupt, or an exception irrespective of the mode. 
 2.Making the IDLE instruction supervisor only 
 The IDLE instruction can be made supervisor only by setting STRICT bit of SYSCFG register. If IDLE instruction is executed in USER mode ,exception will be generated. This will help in improving user mode security in RTOS based system.

Question 16

Digital watch code for RTC

Accepted Answer

The attached code implements the digital watch functionality using the RTC. For the ease of use,the code accepts the date and time in Sec:Min:Hr DD/MM/YR format and get the date and time from RTC in same format which can be easily understood by the end user.

Attachments:

5277.RTC_DigitalWatchFunction.zip

Question 17

How to use the Signtool Utility to encrypt and sign the unsigned bootstream (loader file generated for an application, example:bootstream.ldr)

Accepted Answer

Q: How to use the Signtool Utility to encrypt and sign the unsigned bootstream (loader file generated for an application, example:bootstream.ldr)? -------------- A: Signtool Utility comes along with the CCES package which can be used to sign and encrypt the unsigned loader stream and make it secure. In order to do this, once we have generated the unsigned bootstream through CCES in binary format following commands can be used to sign and encrypt the bootstream: Now, how to use SignTool: To generate a Public/Private key pair Signtool genkeypair –algo ecdsa224 –outfile 2. To get the public key from the key pair file Signtool getkey –key -type BLKey –outfile 3. To sign a boot image (BLp) Signtool sign –type BLp –prikey -infile -outfile 4. To sign and encrypt a boot image (BLx) Signtool sign –type BLx –prikey -enckey -infile -outfile Note: is 128bit encryption key that is used for encryption and decryption 5. To sign and encrypt a boot image (BLw) Signtool sign –type BLx –prikey -enckey -wrapkey -infile -outfile Note: holds another 128-bit key which is used to “wrap” the encryption key used to encrypt the boot stream. Now below command lines shows the same steps used above for a given unsigned bootstream (bootstream.ldr) to add more clearity: Generate an ECDSA key pair using signtool . "C:\Analog Devices\CrossCore Embedded Studio 1.1.0\signtool.exe" genkeypair -algo ecdsa224 -outfile keypair.bin 2. Extract the public key from above generated ECDSA key pair. "C:\Analog Devices\CrossCore Embedded Studio 1.1.0\signtool.exe" getkey -key keypair.bin -type BLKey -outfile pubkey.bin 3. Now to just sign the unsigned bootstream (bootstream.ldr) use the following command: "C:\Analog Devices\CrossCore Embedded Studio 1.1.0\signtool.exe" sign -type BLp -prikey keypair.bin -infile bootstream.ldr -outfile blp_signed_bootstream.bin 4. In order to sign and encrypt the bootstream, two approaches are available: a. BLx: "C:\Analog Devices\CrossCore Embedded Studio 1.1.0\signtool.exe" sign -type BLx -prikey keypair.bin -enckey aeskey.bin -infile bootstream.ldr -outfile blx_signed_bootstream.dat b. BLw: "C:\Analog Devices\CrossCore Embedded Studio 1.1.0\signtool.exe" sign -type BLw -prikey keypair.bin -enckey aeskey.bin -wrapkey wrapperkey.bin -infile bootstream.ldr -outfile blw_signed_bootstream.dat Now last step required is to program the corresponding encryption/wrapper key and the public key into the OTP for secure booting.

Question 18

ADSP-BF70x application cannot boot using Secure Boot

Accepted Answer

Question: 
 I have a BF70x application which cannot boot in secure mode. The same application boots without issue using non-secure mode 
 
 ----------------------------- 
 Answer: 
 ADSP-BF70x processors support Secure Booting, where the loader stream is digitally signed and/or encrypted using the new signtool utility, and the processor's Boot Kernel decrypts the stream and authenticates the signature before permitting the stream to boot. Silicon anomaly 19000022 describes a problem processing "fill blocks" when booting in secure mode, which causes the boot to fail. 
 To avoid this problem, build the loader stream using the elfloader's -NoFillBlock switch, which can be added under ‘Project: Preferences: C/C++ Build: Settings: CrossCore Blackfin Loader: Additional Options’. 
 There is no problem processing "fill blocks" in non-secure mode. You can build the loader stream using the elfloader’s default of creating “fill blocks” for non-secure booting.

Question 19

Cache Enhancements in Blackfin+ core

Accepted Answer

1. Instruction Cache Way Locking: 
 The instruction cache way locking feature is no longer supported in new Blackfin+ core. 
 2. Direct access to cache and Instruction memory space: 
 Blackin+ processor support new mode called Extended Data Access mode. In this mode , direct access of the L1 Data cache memory, L1 instruction cache memory and L1 instruction memory is allowed. This mode can be enabled by setting ENX bit in L1_DM_DCTL register. Cache Tag memory, Dirty State memory can be directly read from the cache memory space and cache invalidation can be done by directly writing into cache memory. DTEST_COMMAND and ITEST_COMMAND registers which provided a back door access to the cache memory are no longer supported in Blackfin+ core and Run-timer libraries also make use of Extended Data Access mode.

Question 20

Is INIT Code supported in Secure Boot in ADSP-BF707

Accepted Answer

Q: 
 Is INIT Code supported in Secure Boot in ADSP-BF707? 
 -------------- 
 A: 
 For a normal bootstream, the customer can make use of the Init Code in case they want to boot from DDR memory. 
 This is not supported for secure boot stream. Instead of this, the customer can make use of the prebooting options which will configure CGU and DDR from OTP. So we need to program the OTP for this.

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