The Engineering Mind
3D ToF Depth Sensing
Aerospace and Defense (ADEF) System Platforms
Analysis Control Evaluation (ACE) Software
Clock and Timing
Design Tools and Calculators
Direct Digital Synthesis (DDS)
Embedded Vision Sensing
Energy Monitoring and Metering
FPGA Reference Designs
Interface and Isolation
Low Power RF Transceivers
MEMS Inertial Sensors
Motor Control Hardware Platforms
Power By Linear
Precision Technology Signal Chains
Processors and DSP
RF and Microwave
Signal Chain Power (SCP)
Speech Processing Solutions
Wide Band RF Transceivers
Wireless Sensor Networks Reference Library
Processors and DSP
ADSP-BF70x requires membership for participation - click to join
ADSP-BF707 - DDR Memory Test
ADSP-BF70X BLACKFIN PROCESSOR SUPPORT COMMUNITY
Different Wake-up Sources on BF70x
FAQ: ADSP-BF707 Preserve data after RESET
FAQ: ADSP-BF70x application cannot boot using Secure Boot
FAQ: Cache Enhancements in Blackfin+ core
FAQ: Can I pass the output generated from PKA directly to the PKTE module for encryption/decryption
FAQ: Configuring Timer in continuous/single pulse mode
FAQ: CPLB enhancements in Blackfin+ Core
FAQ: Different Wake-up Sources on BF70x
FAQ: Digital watch code for RTC
FAQ: Enhancements in Hardware Loop in Blackfin+ core
FAQ: Enhancements in Supervisor Mode in Blackfin+ core
FAQ: HADC maximum bandwidth
FAQ: Highlights of MSI on BF70x
FAQ: How can I initialize DDR memory device connected to BF70x processor ?
FAQ: How do I access the full memory space of the SPI slave?
FAQ: How L2CTL in BF70x is different than BF60x ?
FAQ: How the System Cross Bar (SCB) in BF70x different than in BF60x ?
FAQ: How to configure MSI IDMAC for Dual Buffer Descriptor Ring mode operation
FAQ: How to re-enable the Core clock on BF70x after gating it
FAQ: How to send data using SPI READY signal
FAQ: How to take the core out of reset on BF70x
FAQ: How to use the Signtool Utility to encrypt and sign the unsigned bootstream (loader file generated for an application, example:bootstream.ldr)
FAQ: Is INIT Code supported in Secure Boot in ADSP-BF707
FAQ: Monitoring Cache Performance on the ADSP-BF70x
FAQ: Performance Enhancements in Blackfin+ core
FAQ: Sample code for HADC on BF70x?
FAQ: UART slave boot BF70x with Higher BAUD rate
FAQ: What are the major differences between DMC module of BF60x and BF70x ?
FAQ: What are the salient features of SPI Host Port on BF70x?
FAQ: What is the effect of bus disabling (RDEN bit) on RTC functionality?
FAQ: What is the Encrypt-Hash and Hash-Decrypt mode in PKTE module
FAQ: What is the purpose of the ownership bit when programming the PKTE module for encryption/hashing?
FAQ: What modes of Encryption and Hashing are supported and how do they make an application secure
FAQ: What Secure Boot Modes are supported in ADSP-BF707?
Getting Started with ADSP-BF70x Processors
How to re-enable the Core clock on BF70x after gating it
Known Errata Against ADSP-BF70x Blackfin+ Datasheet
the secret BF70x documentation
Where can I find power consumption data for BF70x processors?
Privacy & Security Statement
Accept & Continue