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Is SCLK0 always limited to 50MHz when using the SMC?

Category: Datasheet/Specs
Product Number: ADSP-BF707

Hello,

I have a question regarding the static memory controller, and whether or not SCLK0 is always limited by CLKOUT when using it.

I know that the limits for SCLK0 and CLKOUT are 100MHz and 50MHz respectively, and the following statement can be found in the datasheet:

SMC Read Cycle Timing With Reference to SYS_CLKOUT
The following SMC specifications with respect to SYS_CLKOUT are given to accommodate the connection of the SMC to
programmable logic devices. These specifications assume that SYS_CLKOUT is outputting a buffered version of SCLK0 by
setting CGU_CLKOUTSEL.CLKOUTSEL = 0x3. However, SCLK0 must not run faster than the maximum fOCLK specification.

So it is clear that, when using the interface in a synchronous fashion with CLKOUT, SCLK0 will indeed be limited to 50MHz as well.

However, what if the connected memory is asynchronous and I don't actually need CLKOUT? Can I operate the SMC at 100MHz as long as I don't select SCLK0 as the source for CLKOUT?

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  • Hi,

    We are checking on this and will get back to you as soon as possible.

    Regards,
    Nandini C

  • Hi,

    Yes, your understanding is correct. As per the ADSP-BF70x datasheet, SCLK0 is limited to 50MHz when the SMC operates with respect to SYS_CLKOUT.
    As mentioned in the HRM, when using the asynchronous memory, the SMC_B0TIM – SMC_B3TIM registers control the timing characteristics of the asynchronous memory interface using different parameters like setup, hold, or access times for reads and writes. Each of these parameters can be programmed in terms of SCLK0 clock cycles. For more information, please refer the "Static Memory Controller (SMC)" chapter in the ADSP-BF70x HRM manual.

    Regards,
    Nandini C

Reply
  • Hi,

    Yes, your understanding is correct. As per the ADSP-BF70x datasheet, SCLK0 is limited to 50MHz when the SMC operates with respect to SYS_CLKOUT.
    As mentioned in the HRM, when using the asynchronous memory, the SMC_B0TIM – SMC_B3TIM registers control the timing characteristics of the asynchronous memory interface using different parameters like setup, hold, or access times for reads and writes. Each of these parameters can be programmed in terms of SCLK0 clock cycles. For more information, please refer the "Static Memory Controller (SMC)" chapter in the ADSP-BF70x HRM manual.

    Regards,
    Nandini C

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