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How to adjust the time delay between SPI clock and data

Category: Software
Product Number: ADSP BF-70x


Now we want to adjust the sample delay time between SPI clock and data less than one clock 

SPI_DLY only provides 1 SPI_CLK cycle lead or lag.

Is there any software method or register setting that can adjust the SPI transfer delay time in smaller time scale rather than one SPI clock?

Thank you.