Post Go back to editing

How to adjust the time delay between SPI clock and data

Category: Software
Product Number: ADSP BF-70x

Hi,

Now we want to adjust the sample delay time between SPI clock and data less than one clock 

SPI_DLY only provides 1 SPI_CLK cycle lead or lag.

Is there any software method or register setting that can adjust the SPI transfer delay time in smaller time scale rather than one SPI clock?

Thank you.

Parents
  • Hi,

    Can you please confirm whether you are asking the delay between the SPI clock and SPI Slave select signal.

    As in the "Figure 29-4: SPI Timing with Lead and Lag Programming" (Page No: 29–8 (1457 / 2223)), by default there will be ½ SPI_CLK delay between SPI_CLK and SPI_SS.

    The SPI uses the SPI_DLY.LAGX bits to control the timing between the slave select (SPI_SS) signal assertion and the first SPI_CLK edge. The SPI uses the SPI_DLY.LEADX bits to control the timing between the last SPI_CLK edge and deassertion of the SPI_SS signal. The lead and lag timing can be extended by a 1 SPI_CLK duration to ease timing restrictions on the slave device.

    Regards,
    Divya.P

  • Hi Divya,P,

    Thank you for reply. But I am sorry that the delay between SPI clock and SPI Slave select signal is not what we are looking for.

    SPI receive data is sample from the input and shift into he register with serial clock. So we wants to know if it is possible to configure Blackfin to adjust/insert the delay between SPI clock is assert and  receive bit is sampled by software means? Per Figure 30 "Serial Peripheral Interface (SPI) Port—Master Timing" in ADSP-BF70x datasheet (Page 84/114), tSSPID "Data Input Valid to SPI_CLK Edge (Data Input Setup)" is close to the timing parameter that we wants to adjust. Please advise if this timing can be adjusted by software means. 

    Many thanks.

    Gchan.

  • Hi Gchan,

    Thanks for the update.

    Please note that the SPI timings needs to be maintained as per the datasheet. It seems it is not possible to modify tSSPID "Data Input Valid to SPI_CLK Edge (Data Input Setup)"

    Regards,
    Divya.P

  • Hi Divya,P,

    Thank you to confirm the register setting for SPI timing adjustment. Will keep the hardware complying the SPI timing characteristics in the datasheet.

    Regards,

    GChan

Reply Children
No Data