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ADSP-BF700 power sequence

Our customer make first their evaluation board (ES1 board), and they started evaluation their ES1 board.

Currently, they validate power up/down sequence, unfortunately VDD_INT and VDD_EXT power up/down sequence are not same time as below.

In case of power up sequence, VDD_INT is power up before VDD_EXT.

In case of power down sequence, VDD_EXT power down before VDD_INT.

They find out the following description related power up/down sequence in the power management section. 

Therefore, they believe that above power sequence not cause any problem

There are no sequencing requirements for the various power domains, but all
domains must be powered according to the appropriate Specifications
table for processor operating conditions; even if the
feature/peripheral is not used.

Are they correct?

If BF700 has some specification about power up/down sequence like as below, you please let us that.

- Analog Devices recommended power on/off sequence

- A time from VDD_INT power up to VDD_EXT power up

- A time from VDD_INT power down to VDD_EXT power down

- etc

Best regards,


  • Hi Takashima,You may have to strictly follow the "Power-Up Reset Timing" sequencing timing requirement mentioned in the ADSP-BF707 datasheet (page no: 61/116). Table 30 and Figure 9 shows relationship between power supply startup and processor reset timing, related to the clock generation unit (CGU) and reset control unit (RCU).
    As you mentioned, "there is no power supply sequencing requirement for the ADSP-BF70x processor". However, if saving power during power-on is important, bringing up VDD_INT last is recommended. This avoids a small current drain in the VDD_INT domain during the transition period of I/O voltages from 0 V to within the voltage specification. In the meantime for the power domains of peripherals you should adhere "Operating Condition"  mentioned in the Pg.No 50/116 of the ADSP-BF707 datasheet .
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