SMC generates a garbage transactions under some conditions, easily reproducible but absolutely not understandable!
Look at the code:
*(unsigned*)0x70000008 = 0x12345678;
// ssync ();
*(unsigned*)0x7000000C = 0x77777777;
When ssync() between writes is commented out, I see an excess transactions on the bus.
Blue is AMS, yellow is AWE.
We can see the first 32-bit write - 2 AWE pulses, but the next write gives 4 AWE pulses, which is wrong
(remember that the bus is 16 bits wide).
With ssync() inserted, everythyng is always OK:
The further the more strange:
this behaviour depends on the particular addresses! (Even though they all aligned by 4!!)
For example if the second write is to 0x70000010 or 0x7000001C, it looks OK!
Here is the maximally stripped-down project.
Aligning by 16 would be a sledge-hummer to crack a nut :-)))
I use only 4 lower addresses of SMC to communicate with FPGA.