Now, I want to use SPT1 and SPT0 as RX, so I use DMA1 AND DMA2 and two interrupt(adi_int_InstallHandler) , when I use SPT1 or SPT0, it is no problem, but I add another interrupt , the TX is wrong, When I use two interrupt , it need other configure?
Hi,From your mail, I can understand that you are using SPORT0 and SPORT1 as receiver. If you can explain your scenario better, I could help on this. If possible, please explain what are the peripherals involved in your system. Do you face issue in using two SPORT receive interrupts? From where does the SPORT receive data?Regards,Anand Selvaraj
I want to connect two other AD by I2S,so I need SPT1 and SPT0 as RX, one SPT interrupt ID is 31, other is 33, use adi_int_InstallHandler(31,SPORTSRxHandler,NULL,true);adi_int_InstallHandler(33,SPORTSRxHandler,NULL,true); I use two interrupt ，Does the interrupt have priority?
Hi,Yes, interrupts have priority. It is not possible to handle the interrupts simultaneously, since the SEC manages the interrupts according to the priority level (for example SPORT0 has higher priority than SPORT1). For more information please refer the Table 8-2 ADSP-BF70x Interrupt List(Page No: 265 / 2223) in the ADSP-BF70x Hardware reference manual. The link for HRM is given below.www.analog.com/.../BF70x_BlackfinProcessorHardwareReference.pdfRegards,Anand Selvaraj.
thanks， I have read it. I have a doubt: If I want to use SPT0 RX and SPT1 rx at the same time, if I use two interrupt 31 and 33 , dose it have a delay for SPT1 RX? what should i do?
Hi,Sorry for the delayed response.I have tested a simple code for receiving data on two SPORTs at the same time. This code can be directly run on ADSP-BF707 EZ-kit. A negligible delay will be incurred due to SPORTs enabled back to back. But there may not be any issues due to both the SPORT DMAs active in parallel. Though the DMAs are active simultaneously the time when the SPORTs request for the internal bus may vary. In the application code ensure that both the DMAs are not accessing the same internal memory block.The high priority DMA channel affecting the low priority one can happen when most of the high speed DMAs are active in parallel. Assuming you have only SPORTs running in your system, the DMA controller will be able to manage the requests easily since only two SPORT DMAs are active.Please use this code as a reference and see how you get through.