I can not see the Sampling Frequency supported in Datasheet.What is the maximum sampling frequency supported by the BF706?The plan is 768kHz / 32bit support.
Hi Andrew,As per the equation, the number of serial clocks between frame syncs = (SPORT_DIV_A.FSDIV + 1)From this, the following equation can be used to determine the value of SPORT_DIV_A.FSDIV, given the serial clock frequency and the desired frame sync frequency:SPORT_DIV_A.FSDIV = [(SPORT_ACLK ÷ SPORT_AFS) – 1]As per the datasheet of ADSP-BF707, Bit clock and Frame sync can support upto 50 Mhz for both internal and external. Please refer the below image. You can get datasheet from below link,www.analog.com/.../adsp-bf700_bf701_bf702_bf703_bf704_bf705_bf706_bf707.pdf
If you consider SPORT Clock frequency as only 49.152 MHz, the chip can support FS of 768KHz.
Regards,Processor Application Support.
Hi Lalitha S
I guess I did not have enough explanation.
planning as an audio product.
HiFi Model is planned, Up to 768kHz / 32bit will be supported.
Usually, Sampling supported by DSP is 32kHz ~ 192kHz or 384kHz / 24bit. It is necessary to check if it is possible to process 768kHz / 32bit from BF706.
Could you confirm the above?
Hi Andrew,As we already mentioned that the datasheet of ADSP-BF707 says that, Bit clock and Frame sync can support upto 50 MHZ for both internal and external. Please refer the below image.
Please note that, if you are using external clock then the 768kHz framesync rate and 32bit is possible BF706, again that clock should be in limitation as mentioned in the datasheet.Internal clock:If you consider SPORT Clock frequency as only 49.152MHz, the chip can support FS of 768KHZ for I2S.SPORT clock=No of channels* serial word length* frame sync rate = 2*32*768KHZ = 49.152MHZ.Serial Clock:SPORT_CLKDIV= [(SCLK0 ÷ SPORT_ACLK) - 1] = 100MHZ / 49.152MHZ = 2-1 = 1 Frame Sync:SPORT_FSDIV = [(SPORT_ACLK ÷ SPORT_AFS) – 1] = 49.152Mhz / 768Khz = 64-1 = 63Regards,Lalitha.S