have to use double precision(64-bit) internal data representation in lowpass IIR filter. So I need multiplication algorithm (in assembler) 32-bit by 64-bit signed fractional, and the result should be a 64 most significant bits from 96-bit result.
The first operation look like this:
R3:2 = R4*R0(m); // R4 - 32-bit coefficient, R1:0 - 64-bit sample.
where R1 holds 32-bit signed fractional coefficient, and R0 unsigned low 32-bits of 64-bit fractional value, but have problem how to add R3 (signed fractional) to 64-bit result of next multiplication:
A1:0 = R4*R1;
R3 (signed fractional) must be added to unsigned A0(W) part of second result.
Hi Roman,Apologies for the delayed response. This case in ADSP-BF70x community, can you please confirm once which processor are working with? Because, Blackfin processor supports upto dual 16-bit or single 32-bit MAC support per cycle.Regards,Lalitha.SA
I work with BF706 one, and the algorithm is as follows:
/* MPY macro definition *//* R1:0 - 64-bit, R2 - 32-bit */#define mpy32x64 \R3 = R2*R0(m); \R0 = 1; \A1:0 = R2*R1; \A1:0 += R3*R0(is)
Hi Roman,Can you please have a look at Multiply Accumulators (MACs) section in the ADSP-BF7xx Blackfin+ Processor Programming Reference manual. You can find the manual from below link,www.analog.com/.../ADSP-BF70x_Blackfin_Programming_Reference.pdfRegards,Lalitha.S