BF707 SMC (Basic Asynchronous SRAM Write Followed by Read)

Hello
I initialise the SMC bus controller with parameters from "BF70x_BlackfinProcessorHardwareReference.pdf" (Revision 1.0, October 2016, page 10-8)

• Write setup time = 2 cycles
• Write access time = 4 cycles
• Write hold time is = 2 cycles
• Read setup time = 3 cycles
• Read access time = 5 cycles
• Read hold time = 1 cycle
• Turnaround transition time = 2 cycles
• Idle transition time = 0 cycles

There is figure 10-2 from the datasheet : Basic Asynchronous SRAM Write Followed by Read :

There is my C Code :

{
    register unsigned short test;
    #define pFPGA_INDEX    ((volatile unsigned short *)0x70000000)        // SMC0 Bank 0
    #define pFPGA_DATA    ((volatile unsigned short *)0x70000002)        // SMC0 Bank 0

    *pREG_SMC0_B0CTL = 0x00004001;                            // SMC0 Bank 0 Control Register
    *pREG_SMC0_B0TIM = 0x05130422;                            // SMC0 Bank 0 Timing Register
    *pREG_SMC0_B0ETIM = 0x00020200;                            // SMC0 Bank 0 Extended Timing Register

    *pFPGA_INDEX = 0x1111;
    test = *pFPGA_DATA;
}

But instead of 20 ns(2 clocks) the READ is distant from WRITE by 300 ns (!)
What is wrong ?