Simple audio in-out code for the ADSP-BF706 EZ-KIT

Hi Patrick,

Thanks for the assembly code for clock configuration!

I think delay loops after TWI transmit are not save enough.
This is my proposal for ADAU1761 configuration:

void write_CODEC_reg(int8_t codec_address, int16_t reg_address, uint8_t reg_data)
{
    *pREG_TWI0_CTL = 0x8c;                  // Set prescale and enable TWI
    *pREG_TWI0_CLKDIV = 0x3232;             // Set duty cycle
    *pREG_TWI0_MSTRADDR = codec_address;    // Address of CODEC
    *pREG_TWI0_TXDATA8 = reg_address >> 8;  // Address of register to set, MSB
    *pREG_TWI0_MSTRCTL = 0xc1;              // Send three bytes and enable transmit
    while((*pREG_TWI0_MSTRCTL >> 6) != 2);  // Wait until first byte is transmitted
    *pREG_TWI0_TXDATA8 = reg_address;       // Address of register to set, LSB
    while((*pREG_TWI0_MSTRCTL >> 6) != 1);  // Wait until second byte is transmitted
    *pREG_TWI0_TXDATA8 = reg_data;          // Data to write
    while (!(*pREG_TWI0_ISTAT & BITM_TWI_ISTAT_MCOMP));
    *pREG_TWI0_ISTAT |= BITM_TWI_ISTAT_TXSERV;
    *pREG_TWI0_ISTAT |= BITM_TWI_ISTAT_MCOMP;
}

void configure_CODEC()
{
    write_CODEC_reg(0x38, 0x4000, 0x01);    // Enable master clock, disable PLL
    write_CODEC_reg(0x38, 0x400a, 0x0b);    // Set left line-in gain to 0 dB
    write_CODEC_reg(0x38, 0x400c, 0x0b);    // Set right line-in gain to 0 dB
    write_CODEC_reg(0x38, 0x4015, 0x01);    // Set serial port master mode
    write_CODEC_reg(0x38, 0x4017, 0x00);    // Set CODEC default sample rate, 48 kHz
    write_CODEC_reg(0x38, 0x4019, 0x63);    // Set ADC to on, both channels
    write_CODEC_reg(0x38, 0x401c, 0x21);    // Enable left channel mixer
    write_CODEC_reg(0x38, 0x401e, 0x41);    // Enable right channel mixer
    write_CODEC_reg(0x38, 0x4023, 0xe7);    // Set left headphone volume to 0 dB
    write_CODEC_reg(0x38, 0x4024, 0xe7);    // Set right headphone volume to 0 dB
    write_CODEC_reg(0x38, 0x4029, 0x03);    // Turn on power, both channels
    write_CODEC_reg(0x38, 0x402a, 0x03);    // Set both DACs on
    write_CODEC_reg(0x38, 0x40f2, 0x01);    // DAC gets L, R input from serial port
    write_CODEC_reg(0x38, 0x40f3, 0x01);    // ADC sends L, R input to serial port
    write_CODEC_reg(0x38, 0x40f9, 0x7f);    // Enable all clocks
    write_CODEC_reg(0x38, 0x40fa, 0x03);    // Enable all clocks
}

Ah yes. I have only tried release mode in assembly - no compiler optimisation.

These are the fully tested versions of the sample-by-sample
and block-processing examples for the BF706 EZ-KIT Mini.
In the ADC control register, Address 0x4019, Bit 6 (ADCPOL)
is active to avoid negative (inverted) polarity of the input signal.
The block-processing version can be used for FFT based
algorithms like overlap add and overlap save.
The block size can be changed in config.h
The software overhead is < 5%. In release mode more the
95% of the processor cycles can be used for audio processing.

I have added an UART DMA control application to facilitate @PatrickG and @UweS excellent audio examples...The discussion is here : 

BF706 UART DMA Terminal for Audio and FIR filter Control 

Hello Patrick,
the DMA block in-out is issue is finally solved (I hope). After several months of frustration
Mike Smith BF706 2D DMA Audio Loopback  proposed a solution:
2D-DMA for double-buffering. According to my tests this works fine for very large blocks or
even sample by sample. One DMA-interrupt per block is generated and the audio processing
can be done in the RX_interrupt_handler.

I would not have solved this without your posts!
Best regards
Uwe