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ADSP-BF706 Production
This device is a member of the ADSP-BF70x Blackfin Digital Signal Processor (DSP) product family. The new Blackfin+ processor core combines dual-MAC 16...
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ADSP-BF706 on Analog.com

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Simple audio in-out code for the ADSP-BF706 EZ-KIT



		

			

									
					    PatrickG
					
							

			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Dec 15, 2016 
				
			
			
		
    

				
		
    
		    		    
		    
		    	
			
    I have an audio in-out program in C for the ADSP-BF706 EZ-KIT mini, about 80 lines in length. It's simple and very easy to understand. It's also completely self-contained - it doesn't use any of the header files that the "TalkThrough_BF706Mini.c" program uses (supplied with the kit). It includes a basic TWI driver, SPORT0 set up and configuration routine for the on board codec (ADAU1761). With some simple modifications it can be used for filtering, both FIR and IIR. The file is attached. All welcome to use free.
    
 
    PatrickG
    
									
			        
		
    

				
							BF706_audio_inout.pdf
							
        

    
    Tags: 
                                            
                 Audio Signal Processors
                
                                                    
                 pg1
                
                                                    
                 Blackfin Embedded Processors
                
                                                    
                 adsp-bf706
                
                                
            
    
    
    

		
    
			
						
									
									
						
						
			
			
			
			
		
    

        
        

					
    
			
    


    
















    
	
    
	
    
					



			








	
	
	
	



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                on Aug 23, 2017 10:20 AM
            
            
					
        
	
        

		
		
        
					
        Hi UweS,
        
 
        Yes, I forgot to mention that CCES in debug mode automatically sets the PLL clocks to maximum (not mentioned in the literature). The FIR code that I wrote (in assembly), which could handle over 8000 32-bit coefficients (around 13500 for 16-bit) would not work from boot up. Once I had set the clocks explicitly in the code, it worked fine. Here is the code to max the speed:
        
 
        // Set the clocks to maximum
        
 
        R1=0X2000;                
        
 
        [REG_CGU0_CTL]=R1;
        
 
        R1=0X42042442;
        
 
        [REG_CGU0_DIV]=R1;
        
			
        

		
			
	      

		
		
	
        
	
        
		
        
			
		
        
	
        
	
        
		
						
				
				
						
				
				
		
		
        
			
		
        
	
        

        

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                on Aug 23, 2017 10:20 AM
            
            
					
          
	
          

		
		
          
					
          Hi UweS,
          
 
          Yes, I forgot to mention that CCES in debug mode automatically sets the PLL clocks to maximum (not mentioned in the literature). The FIR code that I wrote (in assembly), which could handle over 8000 32-bit coefficients (around 13500 for 16-bit) would not work from boot up. Once I had set the clocks explicitly in the code, it worked fine. Here is the code to max the speed:
          
 
          // Set the clocks to maximum
          
 
          R1=0X2000;                
          
 
          [REG_CGU0_CTL]=R1;
          
 
          R1=0X42042442;
          
 
          [REG_CGU0_DIV]=R1;
          
			
          

		
			
	      

		
		
	
          
	
          
		
          
			
		
          
	
          
	
          
		
						
				
				
						
				
				
		
		
          
			
		
          
	
          

          

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