I'm using BF-609 in one of our Hardware.
After Power ON,the JTAG has been connected to the Hardware and passed the jtag configuration test (scan path) but during debug we got the exception (as attached) at the very first at adi_initComponents() and the application has been halted. I have tried the following options i.e 1. Cleaned and re-built the project. 2. Created new project in the new workspace with default settings of BF609 ,built and loaded using ICE-2000 emulator. I had tried with new project with empty code(just c code with simple for loop) as well as with the available examples provided in the CCES IDE (1.1.0) with our Hardware Card in different workspaces but the code is generating the same exception at the very first at adi_initComponents(). Please post the solution to this exception.
Hello, This issue is handled through private support. To avoid duplication of efforts, you can continue the discussions through private support and we will post the final resolution here. Best Regards,Jithul
Hope you're doing fantastic.
Is there any final resolution for this kind of issue? Perhaps that might help me in troubleshooting my problem.
I'm also getting exception when I attempt to launch the debug perspective.
In my case exception no is 0x21.
Thanks & Regards
Hello,As the issue is not simulated in the Ez-kit, can you please try the below suggestions to avoid exception issue.Since this is memory protection violation issue, we would suggest you to refer the "Memory Protection and Properties" section in Memory Chapter of programming reference manual to get more information on protection attributes of CPLB to isolate the issue.www.analog.com/.../Blackfin_pgr_rev2.2.pdfCan you please see the RETX register to locate the exact failing instruction and the offending instruction can be examined for further insight into the problem.Is the instruction accessing memory which has no valid CPLB definition?Is the instruction performing a memory load/store from/to a misaligned location?Does the pointer or index register point to an invalid memory region? A breakpoint can be set in the vicinity of the instruction that caused the hardware error or exception and the code can be single-stepped while observing the address registers (IxorPx).andler).And so the exceptions can be caused by many different configurations errors and/or emulator settings errors or corruption of the configuration files. We would still recommend you to first try to clean your project, restart CCES, then do a Build and Debug. We would strongly recommend that you should also try to create a new CrossCore Project and use the default settings for the BF60x and the ICE-1000 or ICE-2000.Could you please try booting a simple led blink application on your custom board and let us know what is the behaviour on it, because the compiler may produce the exceptions on run time if any memory attributes misses in the CPLB registers.Are you managing the 'silicon revision setting' as per the processor revision mentioned on the chip in your project? Can you test with 'any' option available in the project properties? Regards,Lalitha.S
Hi Siddhant,Could you please provide more information on below points to assist you better on this.1) Could you please confirm whether any instructions placed in the SDRAM.For instance,#pragma section("seg_ext_data"),void foo_fun ();If yes, could you please try moving these functions into the internal memory and check if that works without giving any exception?2) What have you confirmed using the memtest? Whether you do read and write to all SDRAM memory with different data pattern and frequencies and that got pass. If 'No', could you please do the same and confirm the basic SDRAM access is correct.3) You mentioned in the previous mail that, "changing the SDRAM chip with one from an older batch solves the issue". Could you please confirm what is the the difference between replaced SDRAM part and the one fails.Also, can you please check once your SDRAM initialization as per the memory device. The Excel-Sheet available in the below link will help to calculate the correct SDR-/DDR1-/DDR2-SDRAM Controller settings for the Blackfin processors External Bus Interface Unit (EBIU), as well as for the DDR2-SDRAM controller (DMC) for the latest generation Blackfin processors. Additionally, there are few comments inside the document which should be read as well.Excel sheet can be found in the below mentioned link.https://ez.analog.com/dsp/blackfin-processors/m/file-uploads/359Regards,Lalitha.S