Serial Port Codes on BF60x

Below attached are the simple codes which can be used as reference to understand how Serial Ports (SPORT) on BF60x processors are programmed.

 

Notes:  All the codes are programmed to run on Core-0. An idle code DXE can be loaded into Core-1.

              If wanted to run these codes on core-1, I believe, only SEC programming in the codes will be changed (i.e. SPORT/DMA register settings, programming will be same). Enable Core-1 in the Core-0 code.

             Some of the codes are written to test data transfer between two SPORT halves. So, two SPORT halves settings used could be same. However, note that two SPORT halves can be independently configured with any settings (unless they are paired by SPMUX).

           

  • 1. Configuring SPORT in DSP Serial Mode:

    DSP Serial mode is configured by setting SPORT_CTL.OPMODE and SPORT_MCTL.MCE bits as zero.

    This code shows:

    - How to configure SPORT0 halves in DSP serial mode.

    - How to access SPORT0 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

    attachments.zip
  • 2. Configuring SPORT in I2S mode:

    I2S mode is configured by setting

    • SPORT_CTL.OPMODE = 1,
    • SPORT_CTL.LAFS = 0,
    • SPORT_CTL.RJUST = 0 and
    • SPORT_MCTL.MCE = 0.

    In this mode, following bit are reserved (in bracket, it's value used in I2S mode)

    • SPORT_CTL.FSR (1)
    • SPORT_CTL.FSED (1)

    This attached code shows:

    - How to configure SPORT1 halves in I2S mode.

    - How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

    I2S_mode.zip
  • 3. Configuring SPORT in Left-Justified Mode (LJ mode):

    LJ mode has similar settings as I2S mode. It is configured by setting

    • SPORT_CTL.OPMODE = 1,
    • SPORT_CTL.LAFS = 1,
    • SPORT_CTL.RJUST = 0 and
    • SPORT_MCTL.MCE = 0.

    In this mode, following bit are reserved (in bracket, it's value used in LJ mode)

    • SPORT_CTL.FSR (1)
    • SPORT_CTL.FSED (1)

    This attached code shows:

    - How to configure SPORT1 halves in LJ mode.

    - How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

    LJ_mode.zip
  • 4. Configuring SPORT in Right-Justified Mode (RJ mode):

    RJ mode can be configured similar to LJ mode configuration. It is configured by setting

    • SPORT_CTL.OPMODE = 1,
    • SPORT_CTL.LAFS = 1,
    • SPORT_CTL.RJUST = 1,
    • SPORT_MCTL.MCE = 0
    • SPORT_MCTL.OFFSET = RJ_Delay_Counter

    In this mode, following bit are reserved (in bracket, it's value used in LJ mode)

    • SPORT_CTL.FSR (1)
    • SPORT_CTL.FSED (1)
    • SPORT_CTL.GCLKEN (0)

    This attached code shows:

    - How to configure SPORT1 halves in RJ mode.

    - How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

    RJ_mode.zip
  • 5. Configuring SPORT in Multichannel mode:

    Multichannel mode is configured by setting

    • SPORT_CTL.OPMODE = 0,
    • SPORT_CTL.RJUST = 0 and
    • SPORT_MCTL.MCE = 1.

    In this mode, following bit are reserved (in bracket, it's value used in Multichannel mode)

    • SPORT_CTL.LAFS (x),
    • SPORT_CTL.FSR (1)
    • SPORT_CTL.DIFS(1)
    • SPORT_CTL.GCLKEN (0)

    This attached code shows how to configure SPORT2 halves in Multichannel DMA mode.

    Multichannel_mode.zip