Serial Port Codes on BF60x

1. Configuring SPORT in DSP Serial Mode:

DSP Serial mode is configured by setting SPORT_CTL.OPMODE and SPORT_MCTL.MCE bits as zero.

This code shows:

- How to configure SPORT0 halves in DSP serial mode.

- How to access SPORT0 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

2. Configuring SPORT in I2S mode:

I2S mode is configured by setting

• SPORT_CTL.OPMODE = 1,
• SPORT_CTL.LAFS = 0,
• SPORT_CTL.RJUST = 0 and
• SPORT_MCTL.MCE = 0.

In this mode, following bit are reserved (in bracket, it's value used in I2S mode)

• SPORT_CTL.FSR (1)
• SPORT_CTL.FSED (1)

This attached code shows:

- How to configure SPORT1 halves in I2S mode.

- How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

3. Configuring SPORT in Left-Justified Mode (LJ mode):

LJ mode has similar settings as I2S mode. It is configured by setting

• SPORT_CTL.OPMODE = 1,
• SPORT_CTL.LAFS = 1,
• SPORT_CTL.RJUST = 0 and
• SPORT_MCTL.MCE = 0.

In this mode, following bit are reserved (in bracket, it's value used in LJ mode)

• SPORT_CTL.FSR (1)
• SPORT_CTL.FSED (1)

This attached code shows:

- How to configure SPORT1 halves in LJ mode.

- How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

4. Configuring SPORT in Right-Justified Mode (RJ mode):

RJ mode can be configured similar to LJ mode configuration. It is configured by setting

• SPORT_CTL.OPMODE = 1,
• SPORT_CTL.LAFS = 1,
• SPORT_CTL.RJUST = 1,
• SPORT_MCTL.MCE = 0
• SPORT_MCTL.OFFSET = RJ_Delay_Counter

In this mode, following bit are reserved (in bracket, it's value used in LJ mode)

• SPORT_CTL.FSR (1)
• SPORT_CTL.FSED (1)
• SPORT_CTL.GCLKEN (0)

This attached code shows:

- How to configure SPORT1 halves in RJ mode.

- How to access SPORT1 data registers in Core mode or in DMA mode (How to handle SPORT core and DMA interrupts)

5. Configuring SPORT in Multichannel mode:

Multichannel mode is configured by setting

• SPORT_CTL.OPMODE = 0,
• SPORT_CTL.RJUST = 0 and
• SPORT_MCTL.MCE = 1.

In this mode, following bit are reserved (in bracket, it's value used in Multichannel mode)

• SPORT_CTL.LAFS (x),
• SPORT_CTL.FSR (1)
• SPORT_CTL.DIFS(1)
• SPORT_CTL.GCLKEN (0)

This attached code shows how to configure SPORT2 halves in Multichannel DMA mode.

5. Configuring SPORT in Packed mode:

Packed mode can be configured in same as Multichannel mode programming. Packed mode is configured by setting:

• SPORT_CTL.OPMODE = 1,
• SPORT_CTL.RJUST = 0 and
• SPORT_MCTL.MCE = 1.

In this mode, following bit are reserved (in bracket, it's value used in Packed mode)

• SPORT_CTL.LAFS (x),
• SPORT_CTL.FSR (1)
• SPORT_CTL.DIFS(1)
• SPORT_CTL.GCLKEN (0)

This attached code shows how to configure SPORT2 halves in Packed mode.

7. Companding Test:

The above codes of different operating modes of SPORT do not cover enabling the companding feature.

The attached code here can be used as reference to understand how companded data can be transmitted and received.

In A-law, 12-bit data can be transmitted in 8-bit compressed format; while at the reciver, this data can be expanded to restore it back 12-bit value (though not exact). Similarly, in u-law 13-bit data can be transferred in 8-bit format.

So, this feature is useful when large data is to be communicated with fewer bits.

For more details about companding, refer Hardware Reference manual of processor.

8. PACK Bit Test:

If a serial port is configured as receiver, PACK bit of SPORT control register enables 16-bit to 32-bit packing.

Similarly if configured as transmitter with PACK bit set, the serial port performs 32-bit to 16-bit unpacking while transmitting data.

Setting this bit, helps to double the Serial Port peripheral bus bandwidth because:

• When using SPORT in DMA mode:
  • when Packing is disabled, for SLEN < 16, PSIZE field should be configured as either 0(1byte) or 1(2bytes);
  • but when Packing is enabled, we can configure PSIZE to 2(4bytes).
• When using SPORT (SLEN < 16) in core mode:
  • when packing is enabled, 32-bit data can be written or read from SPORT Data buffers compared to 8-bit or 16-bit data access when packing is disabled.

This newly added feature to Blackfin SPORT is available in SHARC serial ports as well.

Attached simple test code can be used to understand how Packing is performed.

Hi Prashant,

I have met some issue in BF60x SPORT in BF60x ez-lite, would you pls take a look and give some advice. thanks!

I run the sport as serial mode, rx, internal fs, internal clock, active low fs, later fs , gated clock mode. each time core will read 4*32bit from sport and after that it will disable sport in sport rx ISR, after some time, sport will be enabled again.

when I set sport clock to 1.25MHz, and capture the sport fs, sport clock from oscilloscope, the fs and clock runs well, howerver when I raised sport clock to 20MHz, there are more sport clock, about 12 sport clock will be generated even sport is disable, also there are some delay for fs signal to change from active/low to deactive/high.

Here is the picture when sport runs in 1.25MHz

Here is the picture when sport runs in 20MHz, you can see there are more sport clock is generated and more delay from fs to change from low to high.

best regards,

Sue

Hi Sue,

I would say this is expected behavior. When SPORT is configured in receive mode for internal clock, internal FS mode, it will initiate the new transfers whenever it's Rx Buffer is not full. Remember, together with input shift register, the receive data buffers act like a three-location FIFO.

So, in your code, SPORT Rx interrupts core whenever there is new data in Rx buffer and core reads that data in ISR; so transfers will be initiated continuously. So, disabling the SPORT at exact point (at the end of forth transfer in your case) is required which may not be always possible, especially when SPORT is running at high speed. That's what you are observing.

You are disabling SPORT in Rx ISR. Reaching at this disable instruction in the ISR will not be immediately at the end of forth transfer. By the time reaches that instruction, SPORT would have started new transfer. Again it depends on at what clock SPORT is operating.

You are seeing no extra clocks at 1.25MHz, it may be because core reaches the disable instruction before SPORT starts new transfer. At 20MHz you see some clocks; at 40MHz you may see more clocks. However, I disagree that you are seeing these extra clocks after disabling the SPORT. You can confirm this by toggling a flag after disabling the SPORT.

Hope it helps. Let me know if you have any questions.

Thanks,

Prashant