Memory architecture of ADSP-BF609

ADSP-BF609 is a dual core processor.
My questions are :

1.How do we diffrentiate between core 0 & core 1 ?? Is it divided linearly like core 0
first and then core 1 ??

As per Memory map from datasheet ADSP-BF69 ,
Core 0 = L1 instruction SRAM(64KB) = 0xFFA0 0000
Core 0 = L1 instruction SRAM(64KB) = 0xFF61 0000
So is it been differentiated w.r.t address ??

2.Where do we flash the code ??Flash is not mentioned clearly(Which address)

3. "Async Memory Banks" and "DDR2 or LPDDR Memory" are relevant only if
we use external memory ??

Thanks,

Jayapriya

  • 0
    •  Analog Employees 
    on Mar 26, 2013 3:11 AM

    Hi,

    Two core have individual L1 memories which are only accessible to respective cores. If you are asking from programming perspective, CCES(IDDE) allows you to create separate projects for each core. So each core can be independently programmed.

    There is no on-chip flash in BF609 processor. External flash can be connected to ASYNC memory bank.

    Yes, ASYNC and DDR2 banks allow to interface external memory to the processor.

    Regards,

    Nabeel

  • 0
    •  Analog Employees 
    on Mar 26, 2013 3:50 AM

    Hi Jayapriya,

    Are you running the processor standalone or through emulator.

    If it is emulator then code an be loaded int L1 instruction memory of Core 0 and run from there. However if it is standalone processor has to boot the code in some way. Then in that case if you plan to boot from flash memory then Flash is needed.

    Are you using EZKIT or what?

    Regards,

    Nabeel

  • Hi Nabeel ,

    Thanks for the reply.

    But still I  have a doubt regarding placing my code .If not external flash , where do I place my code in linker file??For eg:I want to use core 0 only .

    So which part of core 0 will my code get placed??

    Thanks,

    Jayapriya

  • Hi Nabeel ,

    Yes Im going to use EZKIT.

    So as per your info,I can use L1 instruction SRAM .

    Just before building the code ,making sure that the linker scripts are OK.

    Is there any option to select respective cores in "ADI_CrossCoreEmbeddedStudio" tool ??

    Thanks,

    Jayapriya

  • 0
    •  Analog Employees 
    on Mar 26, 2013 10:50 PM

    Hi,

    Yes, when running in emulator session, code can be loaded directly to L1 memory of core for which the project is built. The default linker file put the code in L1 memory by default unless directed to do otherwise.

    CCES allow to build a separate .dxe for each core. So you can explicitly have the code run on one core you want. However for running the code on Core1, it should be first enabled by core 0.

    Regards,

    Nabeel