Pwm trip

Hi Nabeel,

Finally one doubt. I have configured trip 0 as trip source for channel A with Hardware trip.

I have configured pin 30 for trip0 i.e. PortG 06 bit.

Now should I give active high pulse on this input pin, Trip0.

For testing purpose how to check the trip condition? Should I remove the active high input to generate trip?

Thanks,

Regards,

Kishore K

  • 0
    •  Analog Employees 
    on Jun 2, 2013 11:54 PM

    Hi Kishore,

    I guess you are using PWM1 so for PWM1 TRIP)0 comes on PG06. The trip is an input tap signal so you do not need to configure any FER or MUX register. THE PG06 has to to in GPIO mode.

    Next providing an active low signal to TRIP0 signal will trip the PWM outputs(whichever have trip enabled) e.g if Channel has TRIP0 as source it will be disabled(driven to inactive state) whenever the TRIP0 is low.

    Now the behavior of outputs depends whether the TRIP0 is configure in RESTART mode or FAULT mode. HRM has more details on difference between two.

    Regards,

    Nabeel

  • 0
    •  Analog Employees 
    on Aug 2, 2018 4:53 PM
    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

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